Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections Withdrawal
Applicants’ amendment of Claim 12 is acknowledged. Thus, the rejection under 112(b) is withdrawn.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 9, 12 and 21 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bernstein (U.S. Patent Pub. No. 2009/0108435).
Regarding Claim 1
FIG. 1 of Bernstein discloses an electrical device, comprising: a plurality of layers coupled with column interconnect structures (125), wherein: the plurality of layers includes at least one pair of adjacent layers comprising an active layer (150) and a heat transfer die layer (111), and wherein the column interconnect structures space the active layer and the heat transfer die layer apart to define a cooling channel (175) between opposing external surfaces of the active layer and the heat transfer die layer and among the column interconnect structures; the active layer has a back end of line (BEOL) layer (130); the heat transfer die layer has either no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm.sup.2/W (silicon has thermal conductivity 148-149 W/m-K at room temperature); and a coolant flowable through the cooling channel to contact an external surface of the heat transfer die layer that opposes the active layer [0049]. Furthermore, said resistance is related to the thermal release performance. Therefore, said resistance is considered to be a result effective variable. The claim to a specific resistance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 9
FIG. 1 of Bernstein discloses the active layer (150) has a first side and a second side opposite the first side; a first heat transfer die layer (111) is coupled to the first side by a first plurality of the column interconnect structures; and a second heat transfer die layer (112) is coupled to the second side by a second plurality of the column interconnect structures.
Regarding Claim 12
FIG. 1 of Bernstein discloses a method for constructing an electrical device, the method comprising: creating a first array (123) of a plurality of column interconnect structures, wherein each column interconnect structure of the plurality of column interconnect structures includes at least one through silicon via (TSV); coupling a first side of an active layer (150) to one end of the first array of the plurality of column interconnect structures, wherein the active layer has a back end of line (BEOL) layer (130); coupling a first heat transfer die layer (111) to another end of the first array of the plurality of column interconnect structures such that the first array spaces the active layer from the first heat transfer die layer to define a first cooling channel (175) between opposing external surfaces of the active layer and the first heat transfer die layer and among the column interconnect structures of the first array, wherein the first heat transfer die layer has either no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm2/W (silicon has thermal conductivity 148-149 W/m-K at room temperature); creating a second array (123) of a plurality of column interconnect structures; coupling one end of the second array of the plurality of column interconnect structures to a second side of the active layer opposite the first side; coupling a second heat transfer die layer (112) to another end of the second array of the plurality of column interconnect structures such that the second array spaces the active layer from the second heat transfer die layer and defines a second cooling channel between opposing external surfaces of the active layer and the second heat transfer die layer and among the column interconnect structures of the second array, wherein the second heat transfer die layer has either no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm2/W; and flowing a coolant through the first cooling channel and the second cooling channel such that the coolant contacts an external surface of the first heat transfer die layer that opposes the active layer and an external surface of the second heat transfer die layer that opposes the active layer [0029].
Regarding Claim 21
FIG. 1 of Bernstein discloses the coolant contacts sidewall surfaces of the column interconnect structures.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Chainer (U.S. Patent Pub. No. 2017/0186728) of record, in view of Xie (U.S. Patent No. 5,880,524).
Regarding Claim 1
FIG. 1 of Chainer discloses an electrical device, comprising: a plurality of layers coupled with column interconnect structures (116), wherein: the plurality of layers includes at least one pair of adjacent layers comprising an active layer (104) and a heat transfer die layer (106), and wherein the column interconnect structures space the active layer and the heat transfer die layer apart to define a thermal interface material (114) between opposing external surfaces of the active layer and the heat transfer die layer and among the column interconnect structures;
the active layer (104) having a back end of line (BEOL) layer (112); the heat transfer die layer (106) has either no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm.sup.2/W [0026]. Furthermore, said resistance is related to the thermal release performance. Therefore, said resistance is considered to be a result effective variable. The claim to a specific resistance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Chainer is silent with respect to “a cooling channel between opposing external surfaces of the active layer and the heat transfer die layer and among the column interconnect structures” and “a coolant flowable through the cooling channel to contact an external surface of the heat transfer die layer that opposes the active layer”.
FIG. 1 of Xie discloses a similar electrical device, comprising a cooling channel (120) between opposing external surfaces of the active layer (106) and the heat transfer die layer (layers between 120 and 140); and a coolant flowable through the cooling channel to contact an external surface of the heat transfer die layer that opposes the active layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chainer, as taught by Xie. The ordinary artisan would have been motivated to modify Chainer in the above manner for purpose of reducing heat flux at the surface of high-power semiconductor packages (Col. 1, Lines 55-57 of Xie).
Claim 1 rejected under U.S.C. 103 as being unpatentable over Brunschwiller (U.S. Patent Pub. No. 2017/0179001), in view of Gutala (U.S. Patent Pub. No. 2017/0133298).
Regarding Claim 1
FIG. 1 of Brunschwiller discloses an electrical device, comprising: a plurality of layers coupled with column interconnect structures (108), wherein: the plurality of layers includes at least one pair of adjacent layers comprising an active layer (106) and a heat transfer die layer (112), and wherein the column interconnect structures space the active layer and the heat transfer die layer apart to define a cooling channel (113) between opposing external surfaces of the active layer and the heat transfer die layer and among the column interconnect structures; the heat transfer die layer has either no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm.sup.2/W; and a coolant flowable through the cooling channel to contact an external surface of the heat transfer die layer that opposes the active layer.
Brunschwiller is silent with respect to “the active layer has a back end of line (BEOL) layer”.
FIG. 1 of Gutala discloses a similar electrical device, wherein the active layer (101) has a back end of line (BEOL) layer (118).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Brunschwiller, as taught by Gutala. The ordinary artisan would have been motivated to modify Brunschwiller in the above manner for purpose of mounting IC die on package substrate ([0016] of Gutala).
Claims 1-8 and 11 rejected under 35 U.S.C. 103 as being unpatentable over Chainer, in view of Lu (U.S. Patent Pub. No. 2006/0042825).
Regarding Claim 1
FIG. 1 of Chainer discloses an electrical device, comprising: a plurality of layers coupled with column interconnect structures (116), wherein: the plurality of layers includes at least one pair of adjacent layers comprising an active layer (104) and a heat transfer die layer (106), and wherein the column interconnect structures space the active layer and the heat transfer die layer apart to define a thermal interface material (114) between opposing external surfaces of the active layer and the heat transfer die layer and among the column interconnect structures;
the active layer (104) having a back end of line (BEOL) layer (112); the heat transfer die layer (106) has either no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm.sup.2/W [0026]. Furthermore, said resistance is related to the thermal release performance. Therefore, said resistance is considered to be a result effective variable. The claim to a specific resistance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Chainer is silent with respect to “a cooling channel between opposing external surfaces of the active layer and the heat transfer die layer and among the column interconnect structures” and “a coolant flowable through the cooling channel to contact an external surface of the heat transfer die layer that opposes the active layer”.
FIG. 1 of Lu discloses a similar electrical device, comprising a cooling channel (51-58) between opposing external surfaces of the active layer and the heat transfer die layer (41); and a coolant flowable through the cooling channel to contact an external surface of the heat transfer die layer that opposes the active layer [0037].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chainer, as taught by Lu. The ordinary artisan would have been motivated to modify Chainer in the above manner for purpose of improving cooling efficiency ([0006] of Lu).
Regarding Claim 2
FIG. 1 of Lu discloses a respective cooling channel is defined between each pair of adjacent layers of the plurality of layers.
Regarding Claim 3
Chainer discloses the coolant is a dielectric coolant [0066].
Regarding Claim 4
FIG. 1 of Chainer discloses at least one of the column interconnect structures (116) comprises at least one through silicon via (TSV); and at least one TSV comprises at least one metal layer [0033].
Regarding Claim 5
FIG. 1 of Chainer discloses each of the plurality of layers comprise a substrate (102) including a material selected from the group consisting of silicon, silicon germanium, silicon doped with carbon (Si:C), germanium (Ge), silicon germanium doped with carbon (SiGe:C), silicon carbide, type III-V compound semiconductor materials, and a combination thereof [0025].
Regarding Claim 6
The limitation “a total through thermal resistance of the active layer is more than 2 Cmm.sup.2/W” is related to material property. Chainer discloses an active layer with substantially identical composi-tion (silicon). Where the claimed and prior art products are identi-cal or substantially identical in structure or composi-tion, or are produced by identical or substantially identical processes, a prima facie case of either antici-pation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP2112.01
Regarding Claim 7
FIG. 1 of Lu discloses the cooling channel contacts a single side of active layer.
Regarding Claim 8
Chainer discloses a total through thermal resistance of the heat transfer die layer is less than 2 Cmm.sup.2/W [0026]. Furthermore, said resistance is related to the thermal release performance. Therefore, said resistance is considered to be a result effective variable. The claim to a specific resistance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
is considered to be a process or functional limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113. With respect to “configured to increase the surface area of the at least one heat transfer die layer”, said configuration is related to the thermal release performance. Therefore, said configuration is considered to be a result effective variable. The claim to a specific configuration therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 11
FIG. 10 of Chainer discloses the column interconnect structures comprise a metal without a substrate.
Claims 12-18 rejected under 35 U.S.C. 103 as being unpatentable over Chainer, in view of Vafai (U.S. Patent Pub. No. 2024/0006269).
Regarding Claim 12
FIG. 10 of Chainer discloses a method for constructing an electrical device, the method comprising: creating a first array (116) of a plurality of column interconnect structures, wherein each column interconnect structure of the plurality of column interconnect structures includes at least one through silicon via (TSV); coupling a first side of an active layer (108) to one end of the first array of the plurality of column interconnect structures, wherein the active layer has a back end of line (BEOL) layer (130); coupling a first heat transfer die layer (1006-1) to another end of the first array of the plurality of column interconnect structures such that the first array spaces the active layer from the first heat transfer die layer to define a first thermal interface material (114) between opposing external surfaces of the active layer and the first heat transfer die layer and among the column interconnect structures of the first array, wherein the first heat transfer die layer has either no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm2/W [0026]; creating a second array (116) of a plurality of column interconnect structures; coupling one end of the second array of the plurality of column interconnect structures to a second side of the active layer opposite the first side; coupling a second heat transfer die layer (1006-2) to another end of the second array of the plurality of column interconnect structures such that the second array spaces the active layer from the second heat transfer die layer and defines a second thermal interface material (114) between opposing external surfaces of the active layer and the second heat transfer die layer and among the column interconnect structures of the second array [0023], wherein the second heat transfer die layer has either no BEOL layer or a BEOL layer having a through thermal resistance of less than 2 Cmm2/W. Furthermore, said resistance is related to the thermal release performance. Therefore, said resistance is considered to be a result effective variable. The claim to a specific resistance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Chainer is silent with respect to “flowing a coolant through the first cooling channel and the second cooling channel such that the coolant contacts an external surface of the first heat transfer die layer that opposes the active layer and an external surface of the second heat transfer die layer that opposes the active layer”.
FIG. 7 of Vafai discloses a similar electrical device, comprising flowing a coolant through the first cooling channel (40) and the second cooling channel (41) such that the coolant contacts an external surface of the first heat transfer die layer (58) that opposes the active layer and an external surface of the second heat transfer die layer that opposes the active layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chainer, as taught by Vafai. The ordinary artisan would have been motivated to modify Chainer in the above manner for purpose of improving thermal performance ([0010] of Vafai).
Regarding Claim 13
FIG. 10 of Chainer discloses Chainer discloses the coolant is a dielectric coolant [0066].
Regarding Claim 14
FIG. 1 of Chainer discloses the active layer, the first heat transfer die, and the second heat transfer die each comprise a substrate including one or more materials selected from silicon, silicon germanium, silicon doped with carbon (Si:C), germanium (Ge), silicon germanium doped with carbon (SiGe:C), silicon carbide, type III-V compound semiconductor material and a combination thereof [0025].
Regarding Claim 15
The limitation “a total through thermal resistance of the at least one active layer is more than 2 Cmm.sup.2/W” is related to material property. Chainer discloses an active layer with substantially identical composi-tion (silicon). Where the claimed and prior art products are identi-cal or substantially identical in structure or composi-tion, or are produced by identical or substantially identical processes, a prima facie case of either antici-pation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP2112.01
Regarding Claim 16
FIG. 1 of Chainer discloses maintaining a total through thermal resistance of the each of the first heat transfer die layer and the second heat transfer die layer less than 2 Cmm.sup.2/W [0026].
Regarding Claim 17
FIG. 10 of Chainer discloses creating a third array (FIG. 9) of a plurality of column interconnect structures; and coupling one end of the third array of the plurality of column interconnect structures to the second heat transfer die layer.
Regarding Claim 18
FIG. 11 of Chainer discloses coupling a third heat transfer die layer to another end of the third array of plurality of column interconnect structures.
Claim 10 rejected under 35 U.S.C. 103 as being unpatentable over Bernstein, in view of Devaux (WO 2022/079381, machine-translation provided).
Regarding Claim 10
Bernstein discloses Claim 1.
Bernstein is silent with respect to “the active layer has an etched surface that increases a surface area of the active layer; and the heat transfer die layer has opposing etched surfaces that increase a surface area of the heat transfer die layer”.
FIG. 6 of Devaux discloses a similar electrical device, wherein the active layer (E) has an etched surface that increases a surface area of the active layer; and the heat transfer die layer has opposing etched surfaces that increase a surface area of the heat transfer die layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Bernstein, as taught by Devaux. The ordinary artisan would have been motivated to modify Bernstein in the above manner for purpose of improving thermal behavior (Page 1, Lines 7-9 of Devaux).
Claim 20 rejected under 35 U.S.C. 103 as being unpatentable over Chainer and Vafai, in view of Leobandung (U.S. Patent Pub. No. 2019/0385928) of record.
Regarding Claim 20
Chainer as modified by Vafai discloses Claim 12.
Chainer as modified by Vafai is silent with respect to “etching the active layer on one side to increase a surface area of the active layer”.
FIG. 8 of Leobandung discloses a similar method, comprising etching the active layer on one side to increase a surface area of the active layer [0032, 0068].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Chainer, as taught by Leobandung. The ordinary artisan would have been motivated to modify Chainer in the above manner for purpose of more efficient heat transfer to the coolant ([0068] of Leobandung).
Pertinent Art
Canaperi (U.S. Patent Pub. No. 2020/0161216), Ivanov (U.S. Patent Pub. No. 2012/0068206), Eid (U.S. Patent Pub. No. 2019/0385933), 20200161216, 20120306088, JP 5983565.
Response to Arguments
Applicants’ arguments with respect to Claims 1 and 12 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
