DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s election of invention I and species I, drawn to Figure 1 and claims 1-5 & 8-11 are acknowledged. Claims 6-7, drawn to an unelected species, is thus withdrawn from further examination. Claims 12-20, drawn to an unelected invention, are also withdrawn from further examination. Claims 1-5 & 8-11 are examined herein.
Election/Restrictions
Applicant's election with traverse of invention I and Species A, drawn to claims 1-5 and 8-11, in the reply filed on 07/17/2026 is acknowledged.
The traversal for invention I is on the ground(s) that invention I and invention II share common elements. This is not found persuasive because the manufacturing method of the chip package provides for various methods of manufacturing the chip package. For example, the height differences for the first and second openings and the separation of the light-shielding layer.
Applicant does not make a specific traversal for species A and species B.
The requirement is still deemed proper and is therefore made FINAL.
Claims 6-7 and 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/17/2026.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2 & 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chien (US Patent Application Publication 2023/0361144A1) in view of Chang (US Patent Application Publication 2023/0360987A1).
Regarding claim 1, Chien (US Patent Application Publication 2023/0361144A1) teaches A chip package (chip package 100, Figure 1), comprising: a semiconductor substrate (chip 120 + wafer 120a + first surface 121 + second surface 123 + sensing area 122, Figure 1, paragraph 0037, teaches The chip has a first surface and a second surface opposite to the first surface, and the first surface faces toward the light transmissive sheet and has a sensing area. The sensing area may be an image sensing area); a light-transmissive plate (light transmissive sheet 110, Figure 1, paragraph 0038, teaches the material of the light transmissive sheet may be glass...The light transmissive sheet and the bonding layer can allow light to pass through to be detected by the sensing area of the chip); a bonding layer (bonding layer 130, Figure 1, paragraph 0037, teaches The bonding layer is located between the chip and the light transmissive sheet, and is configured to connect the chip and the light transmissive sheet) located between the semiconductor substrate and the light-transmissive plate, wherein the semiconductor substrate, the bonding layer, and the light-transmissive plate jointly define a sidewall (sidewall 125 + sidewall 131 + surface 113, Figure 1) including a first region and a second region, the first region extends from the semiconductor substrate to the light-transmissive plate, and the first region is recessed relative to the second region (Figure 1); and a light-shielding layer (insulating layer 140, Figure 1) covering the sidewall and comprising an extending portion, a wide portion, and a narrow portion, wherein the extending portion is located on a surface of the semiconductor substrate facing away from the bonding layer, the wide portion is located on the first region of the sidewall, and the narrow portion is located on the second region of the sidewall, as claimed.
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Chien (US Patent Application Publication 2023/0361144A1) is silent to teach the material of the insulating layer having light-shielding properties.
In an analogous art, Chang (US Patent Application Publication 2023/0360987A1) teaches a protective molding layer with shading properties to prevent glare along the sidewalls (molding layer 31, Figure 1, paragraphs 0022-0023).
Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Chien (US Patent Application Publication 2023/0361144A1) by using the material of the molding layer of Chang (US Patent Application Publication 2023/0360987A1) thereby providing a protective encapsulant capable of blocking light from the sidewalls of the semiconductor substrate.
Regarding claim 2, Chien (US Patent Application Publication 2023/0361144A1) and Chang (US Patent Application Publication 2023/0360987A1) teach the chip package of claim 1, as claimed. Chien (US Patent Application Publication 2023/0361144A1) further teaches wherein the narrow portion of the light- shielding layer is in direct contact with the light-transmissive plate (Figure 1), as claimed.
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Regarding claim 4, Chien (US Patent Application Publication 2023/0361144A1) and Chang (US Patent Application Publication 2023/0360987A1) teach the chip package of claim 1, as claimed. Chien (US Patent Application Publication 2023/0361144A1) further teaches wherein the bonding layer completely covers a surface of the semiconductor substrate facing toward the bonding layer (Figure 1), as claimed.
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Regarding claim 5, Chien (US Patent Application Publication 2023/0361144A1) and Chang (US Patent Application Publication 2023/0360987A1) teach the chip package of claim 4, as claimed. Chien (US Patent Application Publication 2023/0361144A1) further teaches wherein a material of the bonding layer is optical glue (bonding layer 130, Figure 1, paragraph 0038, teaches the bonding layer may be optical clear adhesive), and a thickness of the bonding layer is in a range from 4 μm to 6 μm (thickness H2, Figure 1, MPEP 2144.05(II)(A) states Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.")), as claimed.
Claim(s) 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chien (US Patent Application Publication 2023/0361144A1) and Chang (US Patent Application Publication 2023/0360987A1) in view of Hong (US Patent No 10,388,619).
Regarding claim 10, Chien (US Patent Application Publication 2023/0361144A1) teach the chip package of claim 1, as claimed.
Chien (US Patent Application Publication 2023/0361144A1) are silent to teach further comprising: an isolation layer disposed along the surface of the semiconductor substrate facing away from the bonding layer; a redistribution layer located on the isolation layer; and a conductive structure located on the redistribution layer.
In an analogous art, Hong (US Patent No 10,388,619) teaches further comprising: an isolation layer (second dielectric layer 120, Figure 8, col 4, lines 5-12 + 63-64, teaches The second dielectric layer may, for example, comprise one or more of the following: polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimidetriazine (BT), phenolic resin, epoxy, silicone, silicon oxide (SiO2), silicon nitride (Si3N4) and equivalents thereof. The second dielectric layer 120 may also, for example, comprise inorganic materials (e.g., silicon oxide, silicon nitride, etc.)...the second dielectric layer (e.g., a passivation layer)) disposed along the surface of the semiconductor substrate facing away from the bonding layer; a redistribution layer (conductive layer 130, Figure 8, col 4, lines 62-64, teaches a conductive layer (e.g., a redistribution layer) formed on the second dielectric layer (e.g., a passivation layer)) located on the isolation layer; and a conductive structure (interconnection structures 141, Figure 8, col col 4 line 67 - col 5 line 1, teaches interconnection structures (e.g., conductive bumps, etc.)) located on the redistribution layer, as claimed.
Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings Chien (US Patent Application Publication 2023/0361144A1) with the teachings of Hong (US Patent No 10,388,619) thereby having a chip structure with external connection bumps.
Regarding claim 11, Chien (US Patent Application Publication 2023/0361144A1) and Hong (US Patent No 10,388,619) teach the chip package of claim 10, as claimed. Hong (US Patent No 10,388,619) further teaches further comprising: a passivation layer (molding part 150, Figure 8, col 5 lines 59-66, teaches a molded part may be formed to cover some or all of the first dielectric layer, the second dielectric layer, the conductive layer...The molded part (e.g., formed of mold material) may, for example, comprise molding compound, epoxy, various encapsulating materials, etc.) located on the isolation layer and the redistribution layer, and surrounding the conductive structure, wherein the extending portion of the light-shielding layer is covered by the passivation layer, as claimed.
Allowable Subject Matter
Claims 3 & 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: the prior art of record does
not teach or suggest the combination of the wide portion of the light-shielding layer being in direct contact with the semiconductor substrate and the bonding layer in claim 3.
The surface of the narrow portion of the light-shielding layer facing away from the wide portion being coplanar with a surface of the light- transmissive plate facing away from the bonding layer in claim 8.
The thickness of the wide portion of the light-shielding layer is in a range from 25 μm to 30 μm, and a thickness of the narrow portion of the light-shielding layer is in a range from 13 μm to 17 μm in claim 9.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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