DETAILED ACTION
This office action is in response to the application filed on June 24, 2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, pending in this office action are claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kitazume (US 2018/0190637) in view of Pagaila (US 2010/0289126)
With respect to Claim 16, Kitazume shows (Fig. 1-11) most aspects of the current invention including a method of forming a semiconductor package, comprising:
providing a first die (30),
stacking a second die (21) on the first die along a first direction (vertical)
forming a first inductor (22) over the first die,
forming a second inductor (23) over the first die
wherein the first inductor and the second inductor are physically separated
However, Kitazume fails to show wherein the first inductor comprising a plurality of first coils around a first axis, wherein the first axis is substantially perpendicular to the first direction and wherein the second inductor includes a plurality of second coils around a second axis.
On the other hand, and in the same field of endeavor, Pagaila teaches (Fig 5) a method of forming a semiconductor package, comprising a die (122) stacked on a build-up interconnect structure along a first direction (vertical), forming a first inductor (pillars 180a, 180b with core 182) adjacent to the die, wherein the first inductor comprising a plurality of first coils around a first axis, wherein the first axis is substantially perpendicular to the first direction, and further forming a second inductor (pillars 180c, 180d with core 184) adjacent to the die, wherein the second inductor includes a plurality of second coils around a second axis. Pagaila teaches doing so to provide integrated 3D inductors coiled around inductor cores (par 50) which provide the electrical characteristics needed for high frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, matching networks, and tuning capacitors (par 53).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the first inductor comprising a plurality of first coils around a first axis, wherein the first axis is substantially perpendicular to the first direction and wherein the second inductor includes a plurality of second coils around a second axis, in the device of Kitazume, as taught by Pagaila to provide integrated 3D inductors coiled around inductor cores which provide the electrical characteristics needed for high frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, matching networks, and tuning capacitors.
With respect to Claim 18, Pagaila teaches (Fig 5) wherein the second axis is substantially perpendicular to the first direction
With respect to Claim 19, Kitazume shows (Fig. 1-11) wherein the first inductor and the second inductor are disposed at different sides of the second die
With respect to Claim 20, Kitazume shows (Fig. 1-11) wherein the first inductor and the second inductor are disposed at opposite sides of the second die.
Claims 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kitazume (US 2018/0190637) in view of Pagaila (US 2010/0289126) and in further view of Kim (US 2017/0373025).
With respect to Claim 21, Kitazume in view of Pagaila show most aspects of the current invention. However, the combination of references do not show wherein the second axis is different from the first axis.
On the other hand, and in the same field of endeavor, Kim teaches (Fig 2,7) a method of forming a semiconductor package, comprising a die (230) on the first die along a first direction (vertical), forming a first inductor (250) adjacent to the die, the first inductor around a first axis that is substantially perpendicular to the first direction and a second inductor (780) around a second axis that is substantially perpendicular to the first direction, wherein the second axis is different from the first axis. Kim teaches the first inductor and the second inductor may be electrically coupled such that they are electrically in parallel with each other.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the second axis is different from the first axis, in the device of Kitazume and Pagaila, as taught by Kim because the first inductor and the second inductor may be electrically coupled such that they are electrically in parallel with each other.
Allowable Subject Matter
Regarding Claim 1, the prior art of record fails to disclose or suggest a method of forming a semiconductor package comprising wherein the second conductive patterns are connected to the first conductive patterns to form a first coil and a second coil surrounding the first coil, the first coil has a first total height extended along the first direction, the second coil has a second total height along the first direction, and the second total height is different from the first total height.
Examiner's comments: the closest prior art references (Gu US 2016/0133614; Pagaila US 2010/0289126; Song US 2016/0141244; Hu US 2019/0148342; Kitazume US 2018/0190637) are all directed in part to semiconductor package comprising a second die stacked on a first die, a first inductor disposed over the first die, wherein the first inductor has a plurality of first coils, similar to the instant inventions.
However, none of the references neither anticipates nor renders obvious the following features of wherein the second conductive patterns are connected to the first conductive patterns to form a first coil and a second coil surrounding the first coil, the first coil has a first total height extended along the first direction, the second coil has a second total height along the first direction, and the second total height is different from the first total height.
Regarding Claim 8, the prior art of record fails to disclose or suggest a method of forming a semiconductor package comprising wherein the through vias, the first conductive layers, the first conductive vias, the second conductive layers and the second conductive vias are connected to form an inductor having a first coil and a second coil surrounding the first coil and the first coil and the second coil are around an axis substantially perpendicular to the first direction.
Examiner's comments: the closest prior art references (Gu US 2016/0133614; 17. Song US 2016/0141244; Hu US 2019/0148342; Kitazume US 2018/0190637) are all directed in part to semiconductor package comprising a second die stacked on a first die, a first inductor disposed over the first die, wherein the first inductor has a plurality of first coils, similar to the instant inventions.
However, none of the references neither anticipates nor renders obvious the following features of wherein the through vias, the first conductive layers, the first conductive vias, the second conductive layers and the second conductive vias are connected to form an inductor having a first coil and a second coil surrounding the first coil and the first coil and the second coil are around an axis substantially perpendicular to the first direction.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Q. B./
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814