Prosecution Insights
Last updated: October 02, 2026
Application No. 18/751,382

SEMICONDUCTOR STRUCTURE

Non-Final OA §112§DP
Filed
Jun 24, 2024
Priority
Dec 30, 2019 — divisional of 11/588,031 +1 more
Examiner
MALEK, MALIHEH
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
490 granted / 615 resolved
+11.7% vs TC avg
Minimal +4% lift
Without
With
+3.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
21 currently pending
Career history
635
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
61.7%
+21.7% vs TC avg
§102
23.3%
-16.7% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 615 resolved cases

Office Action

§112 §DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the application filed on 06/24/2024. Currently, claims 1-20 are pending. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Currently, the title has been changed to: “Semiconductor Structure for Flash Memory Device” Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 1, lines 4-5, the recitation “wherein the second gate structure comprises a first layer and a second layer, the first layer is between the second layer and the first gate structure” is ambiguous. The second gate structure comprises the first and second layers, how the first layer is between the second layer and the first gate? The drawings do not appear to show this limitation. In claim 7, line 5, the recitation “the first layer is between the second layer and the first gate structure” is indefinite. It is therefore unclear how this limitation is met, and the drawings do not appear to depict or support the claimed “the first layer is between the second layer and the first gate structure”. The same applies to claim 15. Claims 2-6, 8-14 and 16-20 are included likewise, as they depend from claim 1, 7 and 15 respectively. Appropriate correction is required. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-3 and 6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,588,031 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because: Regarding claim 1, claim 8 of the U.S. Patent No. 11,588,031 B2 discloses the limitations of this claim. Claim 8 of the U.S. Patent No. 11,588,031 B2 is narrower as it also states a select gate and an erase gate. Regarding claims 2, 3, and 6, claims 9, 4, and 18 of U.S. Patent No. 11,588,031 B2 disclose the claimed limitations respectively. Allowable Subject Matter Claims 1-20 are rejected under the 112 rejection described above, but would be allowable if amended to overcome the 112 rejection explained above. Claims 1-3 and 6 are also rejected under the double patenting rejection described above, but would be allowable if amended, or a timely filed terminal disclaimer may be used to overcome the obviousness-type double patenting rejection over the prior patent. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 1, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, the first layer and the second layer comprise a same semiconductor material and same dopants, the first layer has a first dopant concentration, and the second layer has a second dopant concentration, wherein the second gate structure comprises a p-type gate structure, and the second dopant concentration of the second layer is greater than the first dopant concentration of the first layer. Claims 2-6 are included likewise as they depend from claim 1. With respect to claim 7, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, the first layer is between the second layer and the first gate structure, wherein the first layer, the second layer and the third layer comprise a same semiconductor material and same dopants, the first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the first dopant concentration. Claims 8-14 are included likewise as they depend from claim 7. With respect to claim 15, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, the first layer is between the second layer and the first gate structure, and the third layer and the fourth layer are between the first layer and the second layer, and wherein the first layer, the second layer, the third layer and the fourth layer comprise a same semiconductor material and same dopants, the first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the first dopant concentration. Claims 16-20 are included likewise as they depend from claim 15. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. June 27, 2026 /MALIHEH MALEK/Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Jun 24, 2024
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §112, §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740136
SEMICONDUCTOR DEVICE STRUCTURE HAVING GATE DIELECTRIC LAYERS WITH DIFFERENT DIELECTRIC COMPOSITIONS AND METHOD OF FORMING THE SAME
4y 1m to grant Granted Sep 15, 2026
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SEMICONDUCTOR RECTIFIER
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DISPLAY SUBSTRATE AND DISPLAY APPARATUS
2y 7m to grant Granted Aug 25, 2026
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LIGHT EMITTING DIODE PACKAGE
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A SEMICONDUCTOR DEVICE WITH FLOATING MAIN BODY REGION VERTICALLY SEPARTING SOURCE FROM DRAIN, AND METHOD OF FORMING THE SAME
3y 0m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
83%
With Interview (+3.6%)
2y 10m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 615 resolved cases by this examiner. Grant probability derived from career allowance rate.

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