DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0279941 A1 to Huang et al. (hereinafter “Huang”).
Regarding claim 1, Huang discloses a semiconductor structure, comprising:
a substrate;
two or more nanosheet channel layers disposed over a first portion of the substrate (semiconductor device 300 comprising substrate 310, 320 having channel region 336 with first and second horizontal portions disposed over first portion of substrate 310, 320; Fig. 3; paragraphs [0027]); and
a source/drain region disposed over a second portion of the substrate adjacent the first portion of the substrate (source/drain 352, 354 disposed over second portion of substrate 310, 320 adjacent first portion; Fig. 3; paragraph [0027]), the source/drain region comprising a crystalline semiconductor material which transfers a longitudinal stress to the two or more nanosheet channel layers (source/drain 352, 354 may be made of crystalline semiconductor material and induce strain in each horizontal portion of the channel region 336; Fig. 3; paragraphs [0027], [0029]).
Regarding claim 2, Huang discloses the semiconductor structure of claim 1, wherein the second portion of the substrate below the source/drain region comprises an interface with end-of-range damage structures (device 300 is annealed after ion implantation which will create recrystallization of semiconductor material in substrate 310, 320 and associated end-of-range defects; paragraph [0020]).
Regarding claim 3, Huang discloses the semiconductor structure of claim 2, wherein the interface is a distance below a top surface of the substrate adjacent the source/drain region (source/drain are formed by ion implantation into substrate surface creating after annealing an interface therebetween below the surface thereof; paragraph [0020]).
Regarding claim 4, Huang discloses the semiconductor structure of claim 2, wherein the end-of-range damage structures are produced during a recrystallization process that converts an amorphous semiconductor material to the crystalline semiconductor material (device 300 is annealed after ion implantation which will create recrystallization of semiconductor material in substrate 310, 320 and associated end-of-range defects; paragraph [0020]).
Regarding claim 5, Huang discloses the semiconductor structure of claim 2, wherein the end-of-range damage structures comprise a border of amorphous semiconductor material in the substrate surrounded by the crystalline semiconductor material (recrystallization of ion-implanted source/drain are adjacent amorphous semiconductor material; paragraphs [0020], [0044]).
Regarding claim 6, Huang discloses the semiconductor structure of claim 1, wherein the two or more nanosheet channel layers provide channels for a p-type nanosheet transistor, and wherein the crystalline semiconductor material of the source/drain region transfers a compressive longitudinal stress to the two or more nanosheet channel layers (horizontal portions of channel region 336 serve as channel for pMOS device where source/drain 352, 354 induce compressive strain in each horizontal portion of the channel region 336; Fig. 3; paragraphs [0027], [0029]-[0030]).
Regarding claim 7, Huang discloses the semiconductor structure of claim 6, wherein the crystalline semiconductor material comprises silicon germanium (crystalline material may comprise silicon germanium; paragraph [0030]).
Regarding claim 8, Huang discloses the semiconductor structure of claim 6, wherein the crystalline semiconductor material comprises boron-doped silicon germanium (crystalline material may comprise boron-doped silicon germanium; paragraph [0030]).
Regarding claim 9, Huang discloses the semiconductor structure of claim 1, wherein the two or more nanosheet channel layers provide channels for an n-type nanosheet transistor, and wherein the crystalline semiconductor material of the source/drain region transfers a tensile longitudinal stress to the two or more nanosheet channel layers (horizontal portions of channel region 336 serve as channel for nMOS device where source/drain 352, 354 induce tensile strain in each horizontal portion of the channel region 336; Fig. 3; paragraphs [0027], [0029]-[0030]).
Regarding claim 10, Huang discloses the semiconductor structure of claim 9, wherein the crystalline semiconductor material comprises carbon-doped silicon (crystalline material may comprise carbon-doped silicon; paragraph [0026]).
Regarding claim 11, Huang discloses the semiconductor structure of claim 9, wherein the crystalline semiconductor material comprises carbon-doped silicon that is further doped with phosphorus (crystalline material may comprise carbon-doped silicon and phosphorus doped silicon; paragraphs [0026], [0031]).
Regarding claim 12, Huang discloses a semiconductor structure comprising:
a substrate;
two or more nanosheet channel layers disposed over a first portion of the substrate (semiconductor device 300 comprising substrate 310, 320 having channel region 336 with first and second horizontal portions disposed over first portion of substrate 310, 320; Fig. 3; paragraphs [0027]);
a first source/drain region disposed over a second portion of the substrate adjacent a first side of the first portion of the substrate (first source/drain 352 disposed over second portion of substrate 310, 320 adjacent first side of first portion; Fig. 3; paragraph [0027]);
a second source/drain region disposed over a third portion of the substrate adjacent a second side of the first portion of the substrate (second source/drain 354 disposed over third portion of substrate 310, 320 adjacent second side of first portion; Fig. 3; paragraph [0027]);
wherein the first source/drain region and the second source/drain region comprise a stressor material which transfers a longitudinal stress to the two or more nanosheet channel layers (source/drain 352, 354 may be made of crystalline semiconductor material and induce strain in each horizontal portion of the channel region 336; Fig. 3; paragraphs [0027], [0029]).
Regarding claim 16, Huang discloses the semiconductor structure of claim 12, the second portion of the substrate and the third portion of the substrate comprise an interface with end-of-range damage structures a distance below a top surface of the substrate adjacent the first source/drain region and the second source/drain region (device 300 is annealed after ion implantation which will create recrystallization of semiconductor material in substrate 310, 320 and associated end-of-range defects, where source/drains are formed by ion implantation into substrate surface creating after annealing an interface therebetween below the surface thereof; paragraph [0020]).
Regarding claim 17, Huang discloses an integrated circuit comprising:
a semiconductor structure comprising: a substrate; two or more nanosheet channel layers disposed over a first portion of the substrate (semiconductor device 300 comprising substrate 310, 320 having channel region 336 with first and second horizontal portions disposed over first portion of substrate 310, 320; Fig. 3; paragraphs [0027]); and
a source/drain region disposed over a second portion of the substrate adjacent the first portion of the substrate (source/drain 352, 354 disposed over second portion of substrate 310, 320 adjacent first portion; Fig. 3; paragraph [0027]), the source/drain region comprising a crystalline semiconductor material which transfers a longitudinal stress to the two or more nanosheet channel layers (source/drain 352, 354 may be made of crystalline semiconductor material and induce strain in each horizontal portion of the channel region 336; Fig. 3; paragraphs [0027], [0029]).
Regarding claim 18, Huang discloses the integrated circuit of claim 17, wherein the second portion of the substrate below the source/drain region comprises an interface with end-of-range damage structures (device 300 is annealed after ion implantation which will create recrystallization of semiconductor material in substrate 310, 320 and associated end-of-range defects; paragraph [0020]).
Regarding claim 19, Huang discloses the integrated circuit of claim 17, wherein the two or more nanosheet channel layers provide channels for a p-type nanosheet transistor, and wherein the crystalline semiconductor material of the source/drain region transfers a compressive longitudinal stress to the two or more nanosheet channel layers (horizontal portions of channel region 336 serve as channel for pMOS device where source/drain 352, 354 induce compressive strain in each horizontal portion of the channel region 336; Fig. 3; paragraphs [0027], [0029]-[0030]).
Regarding claim 20, Huang discloses the integrated circuit of claim 17, wherein the two or more nanosheet channel layers provide channels for an n-type nanosheet transistor, and wherein the crystalline semiconductor material of the source/drain region transfers a tensile longitudinal stress to the two or more nanosheet channel layers (horizontal portions of channel region 336 serve as channel for nMOS device where source/drain 352, 354 induce tensile strain in each horizontal portion of the channel region 336; Fig. 3; paragraphs [0027], [0029]-[0030]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang.
Regarding claim 13, Huang discloses the semiconductor structure of claim 12, wherein the stressor material comprises a semiconductor material with a crystalline orientation.
Huang fails to explicitly disclose the semiconductor material with a {001} crystalline orientation.
However, Huang already discloses an Si/SOI wafer (see paragraph [0013]) where the industry standard for FinFETs is (100)/{001} orientation.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang in this manner in order to potentially provide . Further, such a orientation is standard in the industry and not novel in the art as evidenced by US 2023/0120656 A1 to Hsu, US 2016/0133697 A1 to Cheng et al., and US 2017/0301786 A1 to Basker et al. which each are related to inducing stress/strain on channel regions.
Regarding claim 14, Huang discloses the semiconductor structure of claim 13, wherein the two or more nanosheet channel layers provide channels for a p-type nanosheet transistor (horizontal portions of channel region 336 serve as channel for pMOS device; Fig. 3; paragraphs [0027], [0029]-[0030]), and wherein the stressor material comprises boron-doped silicon germanium (crystalline material may comprise boron-doped silicon germanium; paragraph [0030]).
Regarding claim 15, Huang discloses the semiconductor structure of claim 13, wherein the two or more nanosheet channel layers provide channels for an n-type nanosheet transistor (horizontal portions of channel region 336 serve as channel for nMOS device; Fig. 3; paragraphs [0027], [0029]-[0030]), and wherein the stressor material comprises carbon-doped silicon (crystalline material may comprise carbon-doped silicon; paragraph [0026]).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2023/0120656 A1 to Hsu, US 2016/0133697 A1 to Cheng et al., and US 2017/0301786 A1 to Basker et al. which each are related to inducing stress/strain in channel regions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
