DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-16, in the reply filed on 8/31/2026 is acknowledged. Claims 17-20 have been canceled. Claims 21-24 are added.
Claim Objections
Claims 1, 22 are objected to because of the following informalities:
Claim 1 recites “the second gate space” in line 6. There is no antecedent basis for the claim terminology. It is interpreted that this is a typographical error of the “second gate spacer”.
Claim 22 recites “, .” at the end.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 9-11, 14 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9-11, 17 of U.S. Patent No. 12027606 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, claim 1 of US 12027606 B2 teaches a semiconductor structure, comprising:
a gate stack over a top surface and a side surface of a semiconductor layer (claim 1 of US 12027606 B2 column 17 lines 48-52);
a first gate spacer abutting a sidewall of the gate stack (claim 1 of US 12027606 B2 column 17 lines 48-52);
a second gate spacer abutting a sidewall of the first gate spacer (claim 1 of US 12027606 B2 column 17 lines 56-59);
a first seal layer over each of the gate stack, the first gate spacer, and the second gate space (claim 1 of US 12027606 B2 column 17 lines 63-65); and
a first void region and a second void region below the first seal layer, wherein the first void region is laterally adjacent the second gate spacer, and the second void region is above the top surface of the gate stack (claim 1 of US 12027606 B2 column 17 line 64 to column 18 line 3).
Claim 9 reads on claim 9 of US 12027606 B2.
Regarding claim 10, claim 10 of US 12027606 B2 teaches a semiconductor structure, comprising:
a gate stack over a top surface and a side surface of a semiconductor layer (claim 10 of US 12027606 B2 column 18 line 31-32);
a first gate spacer along a sidewall of the gate stack (claim 10 of US 12027606 B2 column 18 line 34-36);
a second gate spacer along a sidewall of the first gate spacer (claim 10 of US 12027606 B2 column 18 line 37-40);
a first seal layer extending over the gate stack, the first gate spacer, the second gate spacer (claim 10 of US 12027606 B2 column 18 line 44-46);
a first void region below the first seal layer, wherein the first gate spacer and the second gate spacer interpose the first void and the gate stack (claim 10 of US 12027606 B2 column 18 line 46-48); and
a second void region above the gate stack and contiguous with the first void region (claim 10 of US 12027606 B2 column 18 line 48-50).
Claims 11, 14 read on claims 11, 15 of US 12027606 B2 respectively.
Regarding claim 21, claim 17 of US 12027606 B2 teaches a semiconductor structure, comprising:
a gate stack over a top surface and a side surface of a semiconductor layer (claim 17 of US 12027606 B2 column 19 line 13-16);
at least one dielectric spacer extending along a sidewall of the gate stack (claim 17 of US 12027606 B2 column 19 lines 17-20);
a seal layer over each of the gate stack and the at least one dielectric spacer (claim 17 of US 12027606 B2 column 20 lines 4-5); and
a void below the seal layer, wherein the void extends over an uppermost surface of the at least one dielectric spacer and over the gate stack (claim 17 of US 12027606 B2 column 20 lines 7-11).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “wherein the first seal layer interfaces a top surface of the second gate structure”. There is no antecedent basis for the “second gate structure” in the claim. Since the specification does not disclose a second gate structure, it is unclear how the claim could be interpreted to work with the disclosure. For the purpose of examination, it is interpreted that the claim 4 is automatically satisfied.
Claim 5 recites “a sidewall of the first gate spacer” in line 2 of the claim. It is unclear whether this is the same or different than the “sidewall of the first gate spacer” defined in line 4 of claim 1. It is interpreted that this is the same sidewall.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Breyta et al. (US 2012/0037962 A1) in view of Cheng et al. (US 2011/0278676 A1).
Regarding claim 1, Breyta teaches a semiconductor structure (structure in Fig. 1a of Breyta), comprising:
a gate stack (125 in Fig. 1a) over a top surface of a semiconductor layer (channel region 122);
a first gate spacer (vertical portion of dielectric layer 131 on sidewalls of gate 125) abutting a sidewall of the gate stack;
a first seal layer (134) over each of the gate stack, the first gate spacer, and the second gate space; and
a first void region (portion of air gap 150 on two sides of the gate) and a second void (portion of air gap 150 directly above the gate) region below the first seal layer, wherein the first void region is laterally adjacent the second gate spacer (as defined above), and the second void region is above the top surface of the gate stack (as defined above).
But Breyta does not teach that the gate stack is disposed a side surface of the semiconductor layer; and a second gate spacer abutting a sidewall of the first gate spacer.
Cheng teaches a finfet device (Figs. 1 and 3 of Cheng) comprising: a fin structure (16 in Fig. 1) and a gate structure (20) disposed on top surface and side surface of the fin structure (see Fig. 1); multi-layer gate spacers (56-58 in Fig. 2 of Cheng).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the channel region 122 of Breyta as a fin structure in order to have increased the device density, and to have formed multiple layer spacer in order to increase the protection ability for the spacers.
Regarding claim 2, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the first void region and the second void region are contiguous (as shown in Fig. 1a of Breyta).
Regarding claim 3, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the first void region interfaces a sidewall of the second gate spacer (as shown in 2 of Cheng, and combined in claim 1 above, the spacer 58 is identified as the second gate spacer. Thus, the air gap 150 would be interface with the outer sidewall of the second gate spacer 58 of Cheng).
Regarding claim 4, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 3, and also teaches wherein the first seal layer interfaces a top surface of the second gate structure (as interpreted in 112b rejection above).
Regarding claim 5, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the second void region interfaces a sidewall the first gate spacer (as shown in Fig. 2 of Cheng, the outer sidewall and the top surface of first gate spacer 56 are exposed. As combined in claim 1 above, the top portion of the air gap 150 would be in contact with the top surface and outer sidewall of the first gate spacer 56).
Regarding claim 6, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 5, and also teaches wherein the seal layer interfaces a top surface of the first gate spacer (as combined in claim 1 above, the top portion of the air gap 150 would be in contact with the top surface and outer sidewall of the first gate spacer 56).
Regarding claim 8, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the first void region and the second void region are connected by a void channel (portion of air gap 150 directly over the gate spacers, as shown in Fig. 1a of Breyta) over the first gate spacer and the second gate spacer.
Claims 1, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Breyta in view of Lee et al. (US 2020/0373387 A1).
Regarding claim 1, Breyta teaches a semiconductor structure (structure in Fig. 1a of Breyta), comprising:
a gate stack (125 in Fig. 1a) over a top surface of a semiconductor layer (channel region 122);
a first gate spacer (vertical portion of dielectric layer 131 on sidewalls of gate 125) abutting a sidewall of the gate stack;
a first seal layer (134) over each of the gate stack, the first gate spacer, and the second gate space; and
a first void region (portion of air gap 150 on two sides of the gate) and a second void (portion of air gap 150 directly above the gate) region below the first seal layer, wherein the first void region is laterally adjacent the second gate spacer (as defined above), and the second void region is above the top surface of the gate stack (as defined above).
But Breyta does not teach that the gate stack is disposed a side surface of the semiconductor layer; and a second gate spacer abutting a sidewall of the first gate spacer.
Lee teaches a finfet device (Figs. 1-3 of Lee) comprising: a fin structure (105 in Fig. 1-2); a gate structure (300 in Fig. 2-3) disposed on top surface and side surface of the fin structure (see Fig. 2); where the gate structure includes a high-k gate dielectric layer (280 in Fig. 3 and [0062] of Lee), a metal gate conductor (290), and multi-layer gate spacers (190 in Fig. 3 of Lee).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the channel region 122 of Breyta as a fin structure in order to have increased the device density, and to have formed metal gate structure, as disclosed by Lee, in order to increase the performance of the device.
Regarding claim 7, Breyta in view of Lee teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the gate stack is a high-k dielectric layer ([0062] of Lee) and a metal gate ([0063] of Lee) over the high-k gate dielectric layer, wherein the high-k gate dielectric layer interfaces the second void region (as incorporated, the gate structure 125 of Breyta would be replaced by 300 of Lee. Since the high-k gate dielectric layer 280 of Lee extends all the way up to the top surface of the gate structure, it would interface with the air gap 150 of Breyta).
Regarding claim 9, Breyta in view of Lee teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein a top end of at least one of the first gate spacer or the second gate spacer has a rounded profile (as shown in Fig. 3 of Lee, the outer sidewall spacer has rounded sidewall near the top corner).
Claims 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Breyta in view of Cheng.
Regarding claim 10, Breyta teaches a semiconductor structure (structure in Fig. 1a of Breyta), comprising:
a gate stack (125 in Fig. 1a) over a top surface of a semiconductor layer (122);
a first gate spacer (vertical portion of 131 on sidewalls of 125) along a sidewall of the gate stack;
a first seal layer (134) extending over the gate stack, the first gate spacer;
a first void region (portion of air gap 150 on two sides of the gate) below the first seal layer, wherein the first gate spacer interpose the first void and the gate stack (as shown in Fig. 1a of Breyta); and
a second void region (portion of air gap 150 directly above the gate) above the gate stack and contiguous with the first void region (as shown in Fig. 1a of Breyta).
But Breyta does not teach that the gate stack is over a side surface of the semiconductor layer; and the semiconductor structure comprising: a second gate spacer along a sidewall of the first gate spacer; the first seal layer extending over the second gate spacer; wherein the second gate spacer interpose the first void and the gate stack.
Cheng teaches a finfet device (Figs. 1 and 3 of Cheng) comprising: a fin structure (16 in Fig. 1) and a gate structure (22) disposed on top surface and side surface of the fin structure (see Fig. 1); and multi-layer gate spacers (56-58 in Fig. 2 of Cheng).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the channel region 122 of Breyta as a fin structure in order to have increased the device density, and to have formed multiple layer spacer in order to increase the protection ability for the spacers.
As incorporated, 56 and 58 of Cheng would be identified as the first gate spacer and second gate spacer. As such the first gate spacer and second gate spacer interpose the first void and the gate stack.
Regarding claim 11, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 10, and also teaches wherein the first seal layer is spaced from the first gate spacer (as shown in Fig. 1a of Breyta), the second gate spacer such that the first void region and the second void region are connected by a void channel (portion of 150 of Breyta right above the first and second gate spacers 56 and 58 of Cheng) extending over a top of the first gate spacer and the second gate spacer.
Regarding claim 12, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 10, and also teaches wherein the first void region has a bottom (the bottom surface of void 150 of Breyta extends of the lower surface of outer spacer 58 of Cheng) defined by the second gate spacer.
Regarding claim 13, Breyta in view of Cheng teaches all limitations of the semiconductor structure ofclaim10,wherein the first seal layer includes at least one composition selected from a group consisting of La203, Al203, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al309, TiO2, TaO2, ZrO2, HfO2, Si3N4 (as described in [0039] of Breyta), Y203, AlON, TaCN, and ZrSi.
Regarding claim 14, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 10, and further comprising: a second seal layer (135 in Fig. 1a of Breyta) disposed on the first seal layer.
Regarding claim 15, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 10, and also teaches wherein an upper surface of each of the first gate spacer and the second gate spacer are further from the semiconductor layer than an upper surface of the gate stack (the top surface of the gate 125 of has a silicide layer 126, so the top surface of the gate is lowered than the top surface of the spacers 56 and 58).
Regarding claim 16, Breyta in view of Cheng teaches all limitations of the semiconductor structure of claim 10, and also teaches wherein the semiconductor layer is a fin (as combined in claim 10 above).
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Breyta et al. (US 2012/0037962 A1) in view of Chen et al. (US 2019/0334008 A1).
Regarding claim 21, Breyta teaches a semiconductor structure (structure in Fig. 1a of Breyta), comprising:
a gate stack (125 in Fig. 1a) over a top surface a semiconductor layer (122);
at least one dielectric spacer (131) extending along a sidewall of the gate stack;
a seal layer (134) over each of the gate stack and the at least one dielectric spacer; and
a void (150) below the seal layer, wherein the void extends over an uppermost surface of the at least one dielectric spacer and over the gate stack (as shown in Fig. 1a of Breyta).
But Breyta does not teach that the gate stack is over a side surface of the semiconductor layer.
Chen teaches a finFET device comprising: a gate structure (30 in Fig. 3 of Chen) disposed over the top surface and sidewalls of a fin structure (24).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel region 122 of Breyta into fin structure, as disclosed by Chen, in order to reduce the device footprint.
Regarding claim 22, Breyta in view of Chen teaches all limitations of the semiconductor structure of claim 21, and also teaches wherein a first sidewall (left vertical sidewall of the portion of 131 on the left sidewall of gate 125 in Fig. 1a of Breyta) of the at least one dielectric spacer is defined by a second spacer element (the portion of 131 on the left sidewall of gate 125) and a second sidewall (right vertical sidewall of the portion of 131 on the right sidewall of gate 125) of the at least one dielectric spacer is defined by a first spacer element (portion of 131 on the right sidewall of gate 125), the second sidewall opposing the first sidewall, .
Regarding claim 23, Breyta in view of Chen teaches all limitations of the semiconductor structure of claim 22, and also teaches wherein the void interfaces the first sidewall and the second sidewall (as shown in Fig. 1a of Breyta).
Regarding claim 24, Breyta in view of Chen teaches all limitations of the semiconductor structure of claim 21, and also teaches wherein the uppermost surface of the at least one gate spacer is defined by a top of a first spacer element (left vertical portion of dielectric layer 131 on left sidewall of 125 in Fig. 1a of Breyta) and a second spacer element (right vertical portion of dielectric layer 131 on right sidewall of 125 in Fig. 1a of Breyta).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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