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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8, 12-14, and 17-20 of U.S. Patent No. 12,046,580. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations recited in claims 1-20 of the present invention are disclosed within claims 1-8, 12-14, and 17-20 of U.S. Patent No. 12,046,580.
Application No. 18/752,388 (present invention)
Patent No.: US 12,046,580 (reference)
Claim 1: a method of fabricating a three-dimensional integrated circuit (3D IC) package, comprising: fabricating a cache die using a first technology node, the cache die including a low-dropout (LDO) regulator and a cache memory device; fabricating a compute die using a second technology node, the compute die including a processor; and bonding the cache die and the compute die using one or more first interconnect structures, wherein the compute die is above the cache die in a vertical direction (see claim 17 of U.S. Patent No. 12,046,580).
Claim 17: a method of fabricating a three-dimensional integrated circuit (3D IC) package, comprising: fabricating a cache die using a first technology node, the cache die including a low-dropout (LDO) regulator and a cache memory device; fabricating a compute die using a second technology node, the compute die including a processor… bonding the cache die and the compute die using one or more first interconnect structures, wherein the compute die is above the cache die in a vertical direction.
Claim 2: the method of claim 1, wherein the second technology node has a smaller contacted poly pitch (CPP) and a smaller minimum metal pitch (MMP) than the first technology node (see claim 18 of U.S. Patent No. 12,046,580).
Claim 18. The method of claim 17, wherein the second technology node has a smaller contacted poly pitch (CPP) and a smaller minimum metal pitch (WIMP) than the first technology node.
Claim 3: the method package of claim 1, wherein the second technology node is more advanced than the first technology node (see claim 19 of U.S. Patent No. 12,046,580).
Claim 19: “wherein the second technology node is more advanced than the first technology node”.
Claim 4: the method package of claim 1, wherein the compute die includes a processor (see claim 17, line 7, of U.S. Patent No. 12,046,580).
Claim 17: “the compute die including a processor” (as recited in line 7).
Claim 5: the method package of claim 1, wherein the compute die includes a plurality of voltage islands each having a rectangular shape with power gates located at the long sides of the rectangular shape (see claim 17, lines 7-10, of U.S. Patent No. 12,046,580).
Claim 17: “the compute die including a processor and a plurality of voltage islands each having a rectangular shape with power gates located at the long sides of the rectangular shape” (as recited in lines 7-10).
Claim 6: the method package of claim 1, further comprising: delivering a plurality of output voltages to the compute die (see claim 17, lines 14-15, of U.S. Patent No. 12,046,580).
Claim 17: “delivering a plurality of output voltages to the plurality of voltage islands in the compute die” (as recited in lines 14-15).
Claim 7: the method of claim 4, wherein the processor includes a plurality of processor cores (see claims 1-3 and 4 of U.S. Patent No. 12,046,580).
Claims 1-3, and 4: “wherein the processor includes a plurality of processor cores” (as recited in claim 4).
Claim 8: the method of claim 1, wherein the one or more first interconnect structures are one or more hybrid bonding (HB) structures (see claim 20 of U.S. Patent No. 12,046,580).
Claim 20: “wherein the one or more first interconnect structures are one or more hybrid bonding (HB) structures”.
Claim 9: the method of claim 1, wherein a front side of the compute die is facing a front side of the cache die (see claims 1-3, and 7 of U.S. Patent No. 12,046,580).
Claims 1-3, and 7: “wherein a front side of the compute die is facing a front side of the cache die” (as recited in claim 7).
Claim 10: the method of claim 9, wherein a cache die top metal layer at the front side of the cache die is connected to the one or more of the first interconnect structures, and a compute die top metal layer at the front side of the compute die is connected to the one or more first interconnect structures (see claims 1-3, 7 and 8 of U.S. Patent No. 12,046,580).
Claims 1-3, 7, and 8: ‘wherein a cache die top metal layer at the front side of the cache die is connected to the one or more first interconnect structures, and a compute die top metal layer at the front side of the compute die is connected to the one or more first interconnect structures” (as recited in claim 8).
Claim 11: a three-dimensional integrated circuit (3D IC) package, comprising: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die including a processor and a plurality of voltage islands, each of the plurality of voltage islands having a rectangular shape with power gates located at the long sides of the rectangular shape; and a first interconnect structure connecting the cache die and the compute die and configured to deliver a plurality of output voltages to the plurality of voltage islands (see claims 1 and/or 13 of U.S. Patent No. 12,046,580).
Claim 1 and/or claim 13: “a three-dimensional integrated circuit (3D IC) package, comprising: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor and a plurality of voltage islands, each of the plurality of voltage islands having a rectangular shape with power gates located at the long sides of the rectangular shape; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction and configured to deliver a plurality of output voltages to the plurality of voltage islands” (as recited in claims 1 and 13).
Claim 12: the 3D IC package of claim 11, wherein the compute die is positioned above the cache die (see claim 1, line 5, of U.S. Patent No. 12,046,580).
Claim 1 and/or claim 13: “a compute die above the cache die” (as recited in claim 1, line 5, and claim 13).
Claim 13: the 3D IC package of claim 11, further comprising a plurality of first interconnect structures that include the first interconnect structure (see claim 1, line 10, of U.S. Patent No. 12,046,580).
Claim 1 and/or claim 13: “one or more first interconnect structures” (see claim 1, line 10, and claim 13) (“more first interconnect structures” which includes a plurality of first interconnect structures that include the first interconnect structure, as recited in claim 13 of the present invention).
Claim 14: the 3D IC package of claim 11, wherein the cache die is fabricated using a first technology node, the compute die is fabricated using a second technology node, and the second technology node has a smaller contacted poly pitch (CPP) and a smaller minimum metal pitch (MMP) than the first technology node (see claim 2 and/or claim 14 of U.S. Patent No. 12,046,580).
Claim 2 and/or claim 14: “wherein the cache die is fabricated using a first technology node, the compute die is fabricated using a second technology node, and the second technology node has a smaller contacted poly pitch (CPP) and a smaller minimum metal pitch (MMP) than the first technology node”.
Claim 15: the 3D IC package of claim 11, wherein the processor includes a plurality of processor cores (see claim 4 of U.S. Patent No. 12,046,580).
Claim 4: “wherein the processor includes a plurality of processor cores”.
Claim 16: the 3D IC package of claim 11, wherein the LDO regulator is underneath the processor in the vertical direction (see claim 5 of U.S. Patent No. 12,046,580).
Claim 5: “wherein the LDO regulator is underneath the processor in the vertical”.
Claim 17: a three-dimensional integrated circuit (3D IC) package, comprising: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die including a front side facing a front side of the cache die, the compute die including a processor and a plurality of voltage islands, each of the plurality of voltage islands having a rectangular shape with power gates located at the long sides of the rectangular shape; and a hybrid bonding (HB) structure connecting the cache die and the compute die and configured to deliver a plurality of output voltages to the plurality of voltage islands (see claims 1, 6, and 7, of U.S. Patent No. 12,046,580).
Claims 1, 6, and 7: A three-dimensional integrated circuit (3D IC) package, comprising: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor and a plurality of voltage islands, each of the plurality of voltage islands having a rectangular shape with power gates located at the long sides of the rectangular shape; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction and configured to deliver a plurality of output voltages to the plurality of voltage islands (claim 1); “wherein the one or more first interconnect structures are one or more hybrid bonding (HB) structures” (claim 6); and “wherein a front side of the compute die is facing a front side of the cache die” (claim 7).
Claim 18: the 3D IC package of claim 17, wherein a cache die top metal layer at the front side of the cache die is connected to the hybrid bonding structure, and a compute die top metal layer at the front side of the compute die is connected to the hybrid bonding structure (see claims 6 and 8, of U.S. Patent No. 12,046,580).
Claims 6 and 8: “wherein the one or more first interconnect structures are one or more hybrid bonding (HB) structures” (claim 6); and “wherein a cache die top metal layer at the front side of the cache die is connected to the one or more first interconnect structures, and a compute die top metal layer at the front side of the compute die is connected to the one or more first interconnect structures” (claim 8).
Claim 19: the 3D IC package of claim 1, further comprising: a substrate underneath the cache die; and an interconnect structure connecting the cache die and the substrate in the vertical direction (see claim 12 of U.S. Patent No. 12,046,580).
Claim 12: “a substrate underneath the cache die; and one or more second interconnect structures connecting the cache die and the substrate in the vertical direction”.
Claim 20: the 3D IC package of claim 19, wherein the cache die is fabricated using a first technology node, the compute die is fabricated using a second technology node, and the second technology node has a smaller contacted poly pitch (CPP) and a smaller minimum metal pitch (MMP) than the first technology node (see claim 2 of U.S. Patent No. 12,046,580).
Claim 2: “wherein the cache die is fabricated using a first technology node, the compute die is fabricated using a second technology node, and the second technology node has a smaller contacted poly pitch (CPP) and a smaller minimum metal pitch (MMP) than the first technology node”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Chen et al. (US 2021/0082894 A1) disclose in figs. 4-5, 6 a package and a corresponding method comprising: a cache die (comprising elements 10a and 20) comprising a regulator (“semiconductor component” 20 may be a “voltage regulator chip”, para. [0063]) and a memory chip (“semiconductor component” 10a includes “the semiconductor die 100” which may be a “memory chip”, Fig. 5, para. [0053]); and a compute die (see a second adjacent “semiconductor component” 10a comprising a second “semiconductor die 100” which may include “a logic chip” such as “a central processing unit”, Fig. 6, para. [0053]). Chen et al. do not disclose the compute die is above the cache die in a vertical direction, as recited in the claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 August 19, 2026
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