Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-20 are pending and examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 06/24/2024 ("06-24-24 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 06-24-24 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING A VOID IN A CAPACITOR IN A TRENCH AND METHOD FOR FABRICATING THE SAME
A. Prior-are rejections based on Li
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 10-13 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2013/0062677 A1 to Li et al. ("Li").
Fig. 8 of Li has been provided to support the rejection below:
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Regarding independent claim 1, Li teaches a semiconductor device, comprising:
a trench 13 formed in a substrate 2 (para [0020] - “FIGS. 1-8 depict one embodiment of a method of forming a trench structure that includes forming a metal-containing layer 14 on the sidewalls and base of a trench 13 formed in an SOI substrate 1, and then converting the metal-containing layer 14 that is in direct contact with the semiconductor material of the SOI substrate 1 into a metal semiconductor alloy lower electrode 18 having an upper edge U1 that is aligned to the upper surface S1 of the base semiconductor layer 2.”);
a capacitor structure 30 (para [0042] - “The upper electrode 20, node dielectric layer 19 and the metal semiconductor alloy lower electrode 18 provide a trench capacitor 30.”) disposed in the trench 13; and
a void 21 (para [0041] - “a void 21”) located in the capacitor structure 30, wherein a material layer 20 of the capacitor structure 30 is merged in the trench 13 to seal a top end of the void 21 (see Fig. 8).
Regarding claim 2, Li teaches the capacitor structure 30 that comprises:
a bottom electrode layer 18 disposed in the trench 13 and on a top surface of the substrate 2;
a first high dielectric constant dielectric layer 19 disposed on the bottom electrode layer 18; and
a top electrode layer 20 disposed on the first high dielectric constant dielectric layer 19, wherein the top electrode layer 20 is the material layer of the capacitor structure 30.
Regarding claim 3, Li teaches the top electrode 20 that directly surrounds the void 21.
Regarding claim 10, Li teaches the trench 13 that comprises a neck portion, the neck portion is a portion of the trench 13 with a smallest width, and the material layer 20 of the capacitor structure 30 is merged at the neck portion.
Regarding independent claim 11, Li teaches a method for fabricating a semiconductor device, comprising:
forming a trench 13 in a substrate 2 (para [0020] - “FIGS. 1-8 depict one embodiment of a method of forming a trench structure that includes forming a metal-containing layer 14 on the sidewalls and base of a trench 13 formed in an SOI substrate 1, and then converting the metal-containing layer 14 that is in direct contact with the semiconductor material of the SOI substrate 1 into a metal semiconductor alloy lower electrode 18 having an upper edge U1 that is aligned to the upper surface S1 of the base semiconductor layer 2.”); and
forming a capacitor structure 30 (para [0042] - “The upper electrode 20, node dielectric layer 19 and the metal semiconductor alloy lower electrode 18 provide a trench capacitor 30.”) in the trench 13, wherein a material layer of the capacitor structure 30 is merged in the trench 13 to form a void 21 (para [0041] - “a void 21”) in the trench 13, and the material layer 20 seals a top end of the void 21 (see Fig. 8).
Regarding claim 12, Li teaches the forming the capacitor structure 30 in the trench 13 that comprises:
forming a bottom electrode layer 18 in the trench 13 and on a top surface of the substrate 2;
forming a first high dielectric constant dielectric layer 19 on the bottom electrode layer 18; and
forming a top electrode layer 20 on the first high dielectric constant dielectric layer 19, wherein the top electrode layer 20 is the material layer of the capacitor structure 30.
Regarding claim 13, Li teaches the top electrode 20 that directly surrounds the void 21.
Regarding claim 20, Li teaches the trench 13 that comprises a neck portion, the neck portion is a portion of the trench 13 with a smallest width, and the material layer 20 of the capacitor structure 30 is merged at the neck portion.
B. Prior-art rejections based on Kuo
Claim Rejections - 35 USC § 102
Claims 1, 10, 11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2023/0009279 A1 to Kuo ("Kuo").
Fig. 1B of Kuo has been annotated to support the rejection below:
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Regarding independent claim 1, Kuo teaches a semiconductor device, comprising:
a trench T1 (para [0019] - “trench T1”) formed in a substrate 200 (para [0018] - “FIG. 1A is a schematic cross-sectional view of a semiconductor device 20. The semiconductor device 20 includes a substrate 200 in which a doped region 210 is formed.”);
a capacitor structure C1, C2, 292 (para [0018] - “A first MIM capacitor C1…A second MIM capacitor C2…An insulating layer 292”) disposed in the trench T1; and
a void V1 (para [0019] - “one of the voids V1”) located in the capacitor structure C1, C2, 292 wherein a material layer 292 of the capacitor structure C1, C2, 292 is merged in the trench T1 to seal a top end of the void V1 (see Fig. 1B).
Regarding claim 10, Kuo teaches the trench T1 that comprises a neck portion NP, the neck portion is a portion of the trench T1 with a smallest width, and the material layer 292 of the capacitor structure C1, C2, 292 is merged at the neck portion NP.
Regarding independent claim 11, Kuo teaches a method for fabricating a semiconductor device, comprising:
forming a trench T1 (para [0019] - “trench T1”) in a substrate 200 (para [0018] - “FIG. 1A is a schematic cross-sectional view of a semiconductor device 20. The semiconductor device 20 includes a substrate 200 in which a doped region 210 is formed.”); and
forming a capacitor structure C1, C2, 292 (para [0018] - “A first MIM capacitor C1…A second MIM capacitor C2…An insulating layer 292”) in the trench T1, wherein a material layer 292 of the capacitor structure C1, C2, 292 is merged in the trench T1 to form a void V1 (para [0019] - “one of the voids V1”) in the trench T1, and the material layer 292 seals a top end of the void (see Fig. 1B).
Regarding claim 20, Kuo teaches the trench T1 that comprises a neck portion NP, the neck portion is a portion of the trench T1 with a smallest width, and the material layer 292 of the capacitor structure C1, C2, 292 is merged at the neck portion NP.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 4.
Claims 5-9 are allowable for depending on the allowable claim 4.
Claim 14 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 14.
Claims 15-19 are allowable for depending on the allowable claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2025/0210508 A1 to Yu et al.
Pub. No. US 2024/0405062 A1 to Kim et al.
Pub. No. US 2018/0203314 A1 to Sugimoto
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 25 September 2025
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
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