DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6-11 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 2023/0109077), (hereinafter, Cheng).
PNG
media_image1.png
375
627
media_image1.png
Greyscale
RE Claim 1, Cheng discloses a semiconductor memory structure with possible magnetic memory “MRAM”, resistive memory “RRAM”, PCRAM, ReRAM or other non-volatile memory devices. Cheng discloses in FIGS. 1-11 a resistive random access memory device, comprising:
a substrate “semiconductor substrate” [0034];
a first inter-layer dielectric (ILD) layer 101 disposed on the substrate [0034];
a first interconnect structure 107 “fill layer” disposed in the first ILD layer 101, referring to FIGS. 1 and 11;
a capping layer 103 “first capping layer” disposed on the first interconnect structure 107 and the first ILD layer 101, referring to FIGS. 1 and 11 [0035];
an intermediate dielectric layer 105 disposed on the capping layer 103, referring to FIGS. 2 and 11 [0047];
a conductive via 109/110 disposed in the capping layer 103 and the intermediate dielectric layer 105, referring to FIGS. 1 and 11 [0048],
wherein the conductive via 109/110 is electrically coupled to the first interconnect structure 107, referring to FIGS. 1 and 11;
a resistive switching element “memory” 112/113/114, referring to FIGS. 6 and 11 [0034 and 0038] disposed on the conductive via 109/110, wherein the resistive switching element 112/113/114 comprises a bottom electrode layer 112, a top electrode layer 114, and a resistive switching material layer 113 [0034] interposed between the top electrode layer 114 and the bottom electrode layer 112. Since the resistive memory is an alternative type of memories that can be used for the aforementioned memory structure, the resistive memory element/material is met;
a hard mask layer 121 “encapsulation layer” [0045] disposed on the resistive switching element 112/113/114, referring to FIGS. 7, 8 and 11. It is the examiner position that the encapsulation layer 121 is functionally equivalent to an etch stopping layer, since etching the layer 121 is performed relative to the top electrode 114 of the resistive memory stack, referring to FIG. 8, hence the claimed limitation is met; and
a second interconnect structure 145b disposed on the hard mask layer 121 and the resistive switching element 112/113/114,
wherein the second interconnect structure 145b comprises a lug portion, referring to FIG. 11, as annotated above, that is in direct contact with an upper sidewall of the top electrode layer 114 of the resistive switching element 112/113/114.
RE Claim 6, Cheng discloses a resistive random access memory device, wherein the hard mask layer 121 comprises a silicon oxide layer or a silicon nitride layer [0145].
RE Claims 7 and 8, Cheng discloses a resistive random access memory device, wherein the conductive via 109/110 comprises a barrier layer 109 and a tungsten layer on the barrier layer 109 [0030]; it is the examiner position that the layer 109, which is made of titanium nitride is functionally equivalent to a barrier layer, hence meeting the claimed limitation.
RE Claim 9, Cheng discloses a resistive random access memory device, wherein the capping layer 103 comprises silicon carbonitride (SiCN), which a nitrogen-doped silicon carbide (NDC) layer [0033].
RE Claim 10, Cheng discloses a resistive random access memory device, wherein the intermediate dielectric layer 105 comprises a TEOS-based silicon oxide layer [0034].
RE Claim 11, Cheng discloses a semiconductor memory structure with possible magnetic memory “MRAM”, resistive memory “RRAM”, PCRAM, ReRAM or other non-volatile memory devices and a method of making the same method for forming. Cheng discloses in FIGS. 1-11 a method for forming a resistive random access memory device, comprising:
providing a substrate “semiconductor substrate” [0034];
forming a first inter-layer dielectric (ILD) layer 101 disposed on the substrate [0034];
forming a first interconnect structure 107 “fill layer” disposed in the first ILD layer 101, referring to FIGS. 1 and 11;
forming a capping layer 103 “first capping layer” disposed on the first interconnect structure 107 and the first ILD layer 101, referring to FIGS. 1 and 11 [0035];
forming an intermediate dielectric layer 105 disposed on the capping layer 103, referring to FIGS. 2 and 11 [0047];
forming a conductive via 109/110 disposed in the capping layer 103 and the intermediate dielectric layer 105, referring to FIGS. 1 and 11 [0048],
wherein the conductive via 109/110 is electrically coupled to the first interconnect structure 107, referring to FIGS. 1 and 11;
forming a resistive switching element “memory” 112/113/114, referring to FIGS. 6 and 11 [0034 and 0038] disposed on the conductive via 109/110, wherein the resistive switching element 112/113/114 comprises a bottom electrode layer 112, a top electrode layer 114, and a resistive switching material layer 113 [0034] interposed between the top electrode layer 114 and the bottom electrode layer 112. Since the resistive memory is an alternative type of memories that can be used for the aforementioned memory structure, the resistive memory element/material is met;
forming a hard mask layer 121 “encapsulation layer” [0045] disposed on the resistive switching element 112/113/114, referring to FIGS. 7, 8 and 11. It is the examiner position that the encapsulation layer 121 is functionally equivalent to an etch stopping layer, since etching the layer 121 is performed relative to the top electrode 114 of the resistive memory stack, referring to FIG. 8, hence the claimed limitation is met; and
forming a second interconnect structure 145b disposed on the hard mask layer 121 and the resistive switching element 112/113/114,
wherein the second interconnect structure 145b comprises a lug portion, referring to FIG. 11, as annotated above, that is in direct contact with an upper sidewall of the top electrode layer 114 of the resistive switching element 112/113/114.
RE Claim 16, Cheng discloses a method of forming a resistive random access memory device, wherein the hard mask layer 121 comprises a silicon oxide layer or a silicon nitride layer [0145].
RE Claims 17 and 18, Cheng discloses a method of forming a resistive random access memory device, wherein the conductive via 109/110 comprises a barrier layer 109 and a tungsten layer on the barrier layer 109 [0030]; it is the examiner position that the layer 109, which is made of titanium nitride is functionally equivalent to a barrier layer, hence meeting the claimed limitation.
RE Claim 19, Cheng discloses a method of forming a resistive random access memory device, wherein the capping layer 103 comprises silicon carbonitride (SiCN), which a nitrogen-doped silicon carbide (NDC) layer [0033].
RE Claim 20, Cheng discloses a method of forming a resistive random access memory device, wherein the intermediate dielectric layer 105 comprises a TEOS-based silicon oxide layer [0034].
Allowable Subject Matter
Claims 2-5 and 12-15 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, Hsieh et al. (US 2018/0175284) disclose an integrated circuits and methods for making the same with magnetic tunnel junction (MTJ) structures are provided. An exemplary method for fabricating an integrated circuit includes forming an MTJ structure including a top electrode layer. The MTJ structure has a first sidewall and a second sidewall separated from the first sidewall by a first width. The method includes forming a conductive etch stop on the top electrode layer. The conductive etch stop has a second width greater than the first width. The method also includes depositing dielectric material over the conductive etch stop and the MTJ structure. The method further includes etching the dielectric material to form a trench exposing the conductive etch stop. Also, the method includes forming a conductive via in the trench over and in electrical communication with the conductive etch stop.
DUTTA et al. (US 2020/0274066) disclose a semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.
WANG et al. (US 2021/0013403) disclose a resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
Prosecution Insights