DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 10, 12, 13, 16, 17 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 16 and 17 of U.S. Patent No. US Pat. 11,621,197 (hereinafter “Pat-197”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-197 discloses all the claimed limitations. See rejection below.
Regarding Claim 10, Pat-197 discloses a semiconductor device, comprising: a first channel region (a first plurality of channel members; see claim 16); a first source/drain feature abutting the first channel region (see claim 16); a first gate structure engaging (wrapping) the first channel region (see claim 16); a second channel region (a second plurality of channel members; see claim 16); a second source/drain feature abutting the second channel region (see claim 16); a second gate structure engaging (wrapping) the second channel region (see claim 16); and an isolation feature includes a first portion stacked between the first and second gate structures and a second portion stacked between the first and second source/drain features (see claim 16), wherein a top surface of the first portion of the isolation feature is above a top surface of the second portion of the isolation feature (see claim 16).
Regarding Claim 12, Pat-197 discloses further comprising: a first backside dielectric feature, wherein the first channel region is disposed on the first backside dielectric feature (see claim 16); and a second backside dielectric feature, wherein the second channel region is disposed on the second backside dielectric feature (see claim 16).
Regarding Claim 13, Pat-197 discloses wherein the first source/drain feature is disposed on the first backside dielectric feature (see claim 16), and wherein the second source/drain feature is disposed on the second backside dielectric feature (see claim 16).
Regarding Claim 16, Pat-197 discloses wherein the isolation feature includes an air gap stacked between the first and second gate structures (see claim 17).
Regarding Claim 17, Pat-197 discloses a method, comprising: providing a workpiece including a frontside and a backside (see claim 1), the workpiece including a substrate (see claim 1), a first channel region (a first plurality of channel members) over a first portion of the substrate (see claim 1), a second channel region (a second plurality of channel members) over a second portion of the substrate (see claim 1), a first gate structure engaging the first channel region (see claim 1), a second gate structure engaging the second channel region (see claim 1), a dielectric fin (a hybrid fin) disposed between the first and second gate structures (see claim 1), an isolation feature disposed under the dielectric fin and sandwiched between the first and second portions of the substrate (see claim 1), wherein the substrate is at the backside of the workpiece and the first and second gate structures are at the frontside of the workpiece (see claim 1); etching the isolation feature, thereby forming an opening exposing the dielectric fin at the backside of the workpiece (see claim 1); removing the dielectric fin from the opening (see claim 1); and depositing a dielectric material into the opening, thereby forming a gate isolation feature disposed between the first and second gate structures (see claim 1).
Regarding Claim 20, Pat-197 discloses wherein the gate isolation feature includes an air gap trapped therein and disposed between the first and second gate structures (see claim 2).
Claims 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17, 18 and 20 of U.S. Patent No. US Pat. 12,046,516 (hereinafter “Pat-516”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-516 discloses all the claimed limitations. See rejection below.
Regarding Claim 17, Pat-516 discloses a method, comprising: providing a workpiece including a frontside and a backside (see claim 17), the workpiece including a substrate (see claim 17), a first channel region (a first plurality of channel members) over a first portion of the substrate (see claim 17), a second channel region (a second plurality of channel members) over a second portion of the substrate (see claim 17), a first gate structure engaging the first channel region (see claim 17), a second gate structure engaging the second channel region (see claim 17), a dielectric fin disposed between the first and second gate structures (see claim 17), an isolation feature disposed under the dielectric fin and sandwiched between the first and second portions of the substrate (see claim 17), wherein the substrate is at the backside of the workpiece and the first and second gate structures are at the frontside of the workpiece (see claim 17); etching the isolation feature, thereby forming an opening exposing the dielectric fin at the backside of the workpiece (see claim 17); removing the dielectric fin from the opening (see claim 17); and depositing a dielectric material into the opening, thereby forming a gate isolation feature disposed between the first and second gate structures (see claim 17).
Regarding Claim 18, Pat-516 discloses further comprising: forming a metal layer disposed at the frontside of the workpiece and electrically connecting the first and second gate structures (see claim 18); and extending the opening upwardly through the metal layer, such that the metal layer is divided into a first segment above the first gate structure and a second segment above the second gate structure (see claim 18).
Regarding Claim 19, Pat-516 discloses further comprising: replacing the first portion of the substrate and the second portion of the substrate with a first backside dielectric feature and a second backside dielectric feature, respectively (see claim 20), wherein a bottom portion of the gate isolation feature is laterally stacked between the first backside dielectric feature and the second backside dielectric feature (see claim 20).
Allowable Subject Matter
Claims 11, 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 recites a source/drain contact landing on the second source/drain feature, wherein the second portion of the isolation feature is in physical contact with the source/drain contact.
Claim 14 recites the top surface of the first portion of the isolation feature is above top surfaces of the first and second gate structures.
Claim 15 recites a bottom surface of the first portion of the isolation feature is below bottom surfaces of the first and second gate structures.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 1-9 are allowed, and claims 10 and 17 will be allowed after overcoming the nonstatutory double patenting rejections set for the above.
The closest prior art, US Pub. 2019/0164838, discloses a semiconductor device comprising finFET structure (fig. 22A) having a first plurality of channel members 150 (left ones), a second plurality of channel members 150 (right ones), first and second gate structures RG’, source/drain structures 220, and a dielectric feature 300 between the first and second gate structures 150, and between the source/drain structures 220 (figs. 22B and 22C). However, the prior art differs from the present invention because the prior art fails to disclose an isolation feature having specific structure and arrangement recited in claims 1 and 10, and the specific method of forming the isolation feature recited in claim 17.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites an isolation feature laterally stacked between the first backside dielectric feature and the second backside dielectric feature, wherein a bottommost portion of the isolation feature is below bottom surfaces of the first and second gate structures, and a topmost portion of the isolation feature is above top surfaces of the first and second gate structures.
Claim 10 recites an isolation feature includes a first portion stacked between the first and second gate structures and a second portion stacked between the first and second source/drain features, wherein a top surface of the first portion of the isolation feature is above a top surface of the second portion of the isolation feature.
Claim 17 recites an isolation feature disposed under the dielectric fin and sandwiched between the first and second portions of the substrate, wherein the substrate is at the backside of the workpiece and the first and second gate structures are at the frontside of the workpiece; etching the isolation feature, thereby forming an opening exposing the dielectric fin at the backside of the workpiece; removing the dielectric fin from the opening; and depositing a dielectric material into the opening, thereby forming a gate isolation feature disposed between the first and second gate structures.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-9, 11-16 and 18-20 variously depend from claim 1, 10 or 17, so they are allowed or will be allowed for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 June 27, 2026
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