Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The present application is a continuation of a family of related applications that includes a parent application no. 18/307,091 and started with application no. 15/874,541.
Currently, claims 1-20 are pending an examined below.
Information Disclosure Statement (IDS)
Information disclosure statement submitted on 06/25/2024 (“06-25-24 IDS”) is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 06-25-24 IDS is being considered by the examiner.
A. Prior-art rejections based on Ryu
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, 8-10 and 13-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2017/0194239 A1 to Ryu et al. ("Ryu").
Fig. 1 of Ryu has been annotated to support the rejection below:
[AltContent: textbox (CB)][AltContent: arrow][AltContent: textbox (tp1)][AltContent: arrow][AltContent: textbox (CB2)][AltContent: arrow][AltContent: textbox (P2)][AltContent: arrow][AltContent: textbox (tp2)][AltContent: arrow][AltContent: textbox (I3)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Sb)][AltContent: arrow][AltContent: textbox (Sa)][AltContent: arrow][AltContent: textbox (S2)][AltContent: arrow][AltContent: textbox (S1)][AltContent: textbox (Via)][AltContent: arrow][AltContent: arrow][AltContent: textbox (P1)]
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Regarding independent claim 1, Ryu teaches a chip package (see Fig. 1 as annotated above), comprising:
a substrate structure 100, 190 (para [0015] - “The substrate 100”; para [0016] - “conductive pattern 190”) comprising:
a redistribution structure 170, 190 (para [0015] - “a third redistribution structure 170”) having a conductive pad 190; and
an insulating layer 120 (para [0014] - “a first dielectric layer 120”) under the redistribution structure 170, 190;
a first chip 200 (para [0013] - “a semiconductor die 200”) over the redistribution structure 170, 190;
a second chip 400 (para [0037] - “The electronic device 400 may operate separately from the semiconductor die 200 and may include, for example, active or passive elements…off-chip reactive elements such as capacitors or inductors, and/or off-chip resistors, for example.”) under the substrate structure 100, 190, wherein a top portion of the second chip 400 extends into the insulating layer 120 from a bottom surface of the insulating layer 120, the bottom surface faces away from the first chip 200, and a portion P1 of the insulating layer 120 is between the second chip 400 and the redistribution structure 170, 190; and
a first molding layer 300 (para [0013] - “encapsulant 300”) over the redistribution structure 170, 190 and the first chip 200, wherein a first sidewall of the first molding layer 300 and a second sidewall of the redistribution structure 170, 190 are substantially level with each other.
Regarding claim 2, Ryu teaches the portion P1 of the insulating layer 120 that is wider than the second chip 400.
Regarding claim 3, Ryu teaches the substrate structure 100, 190 that further comprises:
a conductive via structure Via or Via, 411 passing through the insulating layer 120, wherein the conductive via structure Via or Via, 411 is under and electrically connected with the conductive pad 90, and the conductive via structure Via or Via, 411 is thicker than the portion P1 of the insulating layer 120.
Regarding claim 4, Ryu teaches a first top surface Sa of the conductive via structure Via or Via, 411 is higher than a second top surface Sb of the portion P1 of the insulating layer 120.
Regarding claim 5, Ryu teaches a first bottom surface of the conductive via structure Via, 411 is lower than a second bottom surface S1 of the portion P1 of the insulating layer 120.
Regarding claim 7, Ryu teaches a second molding layer 121 under the redistribution structure (para [0024] - “a dielectric layer 121”) and (partially) surrounding the insulating layer 120 and the second chip 400.
Regarding independent claim 8, Ryu teaches a chip package (see Fig. 1 as annotated above), comprising:
a redistribution structure 170, 190 (para [0015] - “a third redistribution structure 170”; para [0016] - “conductive pattern 190”) having a conductive pad 190;
a first insulating layer 120 (para [0014] - “a first dielectric layer 120”) under the redistribution structure 170, 190, wherein the first insulating layer 120 has a first portion P1 and a second portion P2, a first bottom surface S1 of the first portion P1 is higher than a second bottom surface S2 of the second portion P2, and a first top surface Sb of the first portion P1 is substantially level with a second top surface Sb of the second portion P2;
a conductive via Via, 411 passing through the second portion P2;
a second insulating layer 140 (para [0015] - “a second dielectric layer 140”) between the first insulating layer 120 and the redistribution structure 170, 190;
a conductive bump CB passing through the second insulating layer 140 and between the conductive pad 190 and the conductive via structure Via, 411;
a first chip 200 (para [0013] - “a semiconductor die 200”) over the redistribution structure 170, 190; and
a second chip 400 (para [0037] - “The electronic device 400 may operate separately from the semiconductor die 200 and may include, for example, active or passive elements…off-chip reactive elements such as capacitors or inductors, and/or off-chip resistors, for example.”) under the first bottom surface S1 of the first portion P1 of the first insulating layer 120.
Regarding claim 9, Ryu teaches the second insulating layer 140 that is in direct contact with the conductive via structure Via, 411 and the first insulating layer 120.
Regarding claim 10, Ryu teaches a third insulating layer I3 between the conductive via structure Via, 411 and the first insulating layer 120, wherein the third insulating layer I3 separates the conductive via structure Via, 411 from the first insulating layer 120.
Regarding claim 13, Ryu teaches a thin portion tp1 of the second insulating 140 that is between the conductive bump CB and the conductive via structure Via, 411, a thick portion tp2 of the second insulating layer 140 is between the first insulating layer 120 and the redistribution structure 170, 190, and the thin portion tp1 is thinner than the thick portion tp2.
Regarding claim 14, Ryu teaches the second insulating layer 140 that is in direct contact with the first top surface Sb of the first portion P1 and the second top surface Sb of the second portion P2 of the first insulating layer 120.
Regarding claim 15, Ryu teaches the second portion P2 of the first insulating layer 120 that has a sidewall facing the second chip 400.
Regarding independent claim 16, Ryu teaches a chip package (see Fig. 1 as annotated above), comprising:
a first insulating layer 160 (para [0015] - “a third dielectric layer 160”);
a second insulating layer 120 under the first insulating layer 160, wherein the first insulating layer 160 is spaced apart from the second insulating layer 120;
a conductive bump CB2 passing through the first insulating layer 160;
a conductive via Via, 411 passing through the second insulating layer 120;
a first chip 200 (para [0013] - “a semiconductor die 200”) over the first insulating layer 160 and electrically connected to the conductive bump CB2; and
a second chip 400 (para [0037] - “The electronic device 400 may operate separately from the semiconductor die 200 and may include, for example, active or passive elements…off-chip reactive elements such as capacitors or inductors, and/or off-chip resistors, for example.”) under the second insulating layer 120, wherein the second chip 400 penetrates into the second insulating layer 120 from a first bottom surface S2 of the second insulating layer 120, the first bottom surface S2 faces away from the first insulating layer 160, and the second chip 400 is spaced apart from the second insulating layer 120.
Regarding claim 17, Ryu teaches the second chip 400 that has a top surface higher than the first bottom surface S2 of the second insulating layer 120 and lower than a lower surface S1 of the second insulating layer 120, and the first bottom surface S2 and the lower surface S1 face away from the first chip 200.
Regarding claim 18, Ryu teaches the second insulating layer 120 that has a sidewall connected between the first bottom surface S2 and the lower surface S1 of the second insulating layer 160, and the sidewall faces the second chip 400.
Regarding claim 19, Ryu teaches a second bottom surface of the second chip 400 that is lower than the first bottom surface S2 of the second insulating layer 120.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Ryu and further in view of Pub. No. US 2015/0228580 A1 to Chen et al. (“Chen”).
Regarding claim 7, Ryu does not teach a second molding layer under the redistribution structure and surrounding the insulating layer and the second chip.
Chen teaches a molding layer 290 under a redistribution structure 212 and surrounding a second insulating layer PN+1 and the second chip 250 (see Fig. 2; para [0060]).
Chen teaches encapsulating a surface mount device 250 with an encapsulant material 290 (para [0060]). Chen teaches that “By encapsulating the surface mount device with an encapsulant material, the surface mount device is protected from moisture and the encapsulant material may provide some relief from thermal and physical stress. The encapsulant may improve the yield of semiconductor packages with the surface mount device.” (para [0061]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the chip package of Ryu by encapsulating the second chip as taught by Chen so as to protect the second chip from moisture as well as thermal and physical stress (Chen, para [0061]).
Regarding claim 20, Ryu does not teach a molding layer between the second chip 400 and the second insulating layer 120.
Chen teaches a molding layer 290 between a second chip 250 and a second insulating layer PN+1 (see Fig. 2; para [0060]).
Chen teaches encapsulating a surface mount device 250 with an encapsulant material 290 (para [0060]). Chen teaches that “By encapsulating the surface mount device with an encapsulant material, the surface mount device is protected from moisture and the encapsulant material may provide some relief from thermal and physical stress. The encapsulant may improve the yield of semiconductor packages with the surface mount device.” (para [0061]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the chip package of Ryu by encapsulating the second chip as taught by Chen so as to protect the second chip from moisture as well as thermal and physical stress (Chen, para [0061]).
B. Prior-art rejection based on Jeon
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 16 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2018/0076103 A1 to Jeon et al. ("Jeon").
Fig. 2 of Jeon has been provided to support the rejection below:
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Regarding independent claim 16, Jeon teaches a chip package (see Fig. 2 as annotated above), comprising;
a first insulating layer 160 (para [0037] - “A second cover layer 160”);
a second insulating layer 310 (para [0028] - “the plurality of base layers 310”; The middle base layer or the bottom two base layers 310 can be attributed to the recited “second insulating layer”) under the first insulating layer 160, wherein the first insulator layer 160 is spaced apart from the second insulating layer 310;
a conductive bump 260 (para [0044] - “A package connection terminal 260”) passing through the first insulating layer 160;
a conductive via structure 328 (para [0029] - “a plurality of conductive vias 328”) passing through the second insulating layer 310;
a first chip 210 (para [0027] - “a second semiconductor chip 210”) over the first insulating layer 160 and electrically connected to the conductive bump 260; and
a second chip 110 (para [0023] - “The first semiconductor chip 110”) under the second insulating layer 310, wherein the second chip 110 penetrates into the second insulating layer 310 from a first bottom surface of the second insulating layer 310, the first bottom surface faces away from the first insulating layer 160, and the second chip 110 is spaced apart from the second insulating layer 310.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claim 1 is provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of the Parent Patent No. 12,046,548 B2 (“ ‘548 Patent”). Although the conflicting claims are not identical, they are not patentably distinct from each other, because the scope of claim 1 of the ‘548 Patent is at least substantially the same with that of claim 1 of the present application.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 is rejected, but would be allowable if it is rewritten in independent form to include all of the limitations of base claim 1 and the intervening claims 3, 4 and 5, or the base claim 1 is amended to include all of the limitations of claim 6 and the intervening claims 3, 4 and 5.
Claim 11 is rejected, but would be allowable if it is rewritten in independent form to include all of the limitations of base claim 8 and the intervening claims 9 and 10, or the base claim 8 is amended to include all of the limitations of claim 11 and the intervening claims 9 and 10.
Claim 12 is rejected, but would be allowable if it is rewritten in independent form to include all of the limitations of base claim 8 and the intervening claims 9 and 10, or the base claim 8 is amended to include all of the limitations of claim 12 and the intervening claims 9 and 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2019/0287956 A1 to Raorane et al.
Pub. No. US 2015/0228580 A1 to Chen et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 07 July 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
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