DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 25, 2024 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of U.S. Patent No. 12,051,735. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent recite each limitation of the instant claims as detailed below.
Instant Application
US Pat. No. 12,051,735
10. A structure comprising: shallow trench isolation regions; a semiconductor fin protruding higher than top surfaces of the shallow trench isolation regions; a gate stack on a top surface and sidewalls of the semiconductor fin; a dielectric isolation region separating the gate stack into a first portion and a second portion; and a dielectric contact spacer in an upper portion of the dielectric isolation region.
11. A device comprising: shallow trench isolation regions; a semiconductor fin protruding higher than top surfaces of the shallow trench isolation regions; a gate stack on a top surface and sidewalls of the semiconductor fin; a dielectric isolation region cutting the gate stack apart, wherein the dielectric isolation region comprises: a lower portion; and an upper portion over and connected to the lower portion, wherein the upper portion is laterally recessed from an edge of the lower portion; and a dielectric contact spacer contacting sidewalls of both of the lower portion and the upper portion of the dielectric isolation region.
‘735 does not explicitly disclose a dielectric isolation region separating the gate stack into a first portion and a second portion; and a dielectric contact spacer in an upper portion of the dielectric isolation region. However, ‘735 discloses that the dielectric isolation region cuts the gate stack apart and that the dielectric contact spacer contacts sidewalls of upper and lower portions of the dielectric isolation region. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the dielectric isolation region cut of ‘735 would at least cut the gate stack into two portions as they are cut apart and that the dielectric contact space of ‘735 contacting sidewalls of the upper portion of the dielectric isolation region implies that the dielectric contact spacer would be an upper region of the dielectric isolation region.
Allowable Subject Matter
Claims 10-17 would be allowed if applicant submitted a terminal disclaimer to overcome the double patenting rejection of claim 10 above.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Chen (US Pat. No. 12,051,735), Cheng (US Pat. No. 9,704,753), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 10 (from which claims 11-17 depend), a dielectric contact spacer in an upper portion of the dielectric isolation region.
Claims 1-9 and 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Chen (US Pat. No. 12,051,735), Cheng (US Pat. No. 9,704,753), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 1 (from which claims 2-9 depend), wherein an end portion of the first contact plug is in the dielectric isolation region…
Regarding Claim 18 (from which claims 19-20 depend), wherein in a top view of the structure, an end portion of the combined region is in a part of the dielectric isolation region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cheng (US Pat. No. 9,704,753) discloses (Fig. 8A) a gate 802 is separated into two portions by dielectric region 502. Cheng does not disclose a contact plug is in the dielectric region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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