DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendment filed on May 05, 2026 has been entered. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-12, 14-18 and 20) is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Phillips et al. [US 20230194997 A1, hereafter Phillips].
As per Claims 1 and 12, Phillips teaches a die 600 (See fig. 6A-6B) comprising:
an array of circuit elements arranged in a grid spanning a first region and a second region that overlap in an overlap region 641 (Para 73), the array of circuit elements including:
a first set of circuit elements 601 in the overlap region receiving a first lithographic deposition of a first layer as the first layer is deposited using a first reticle of a first pattern in the overlap region and aligned with the first region (Para 72); and
a second set of circuit elements 602 in the overlap region receiving a second lithographic deposition of the first layer as the first layer is deposited using a second reticle of a second pattern in the overlap region and aligned with the second region (Para 72), the first lithographic deposition and the second lithographic deposition do not overlap on a same circuit element in the overlap region (See fig. 6A-6B, Para 72-75).
As per Claims 4-8 and 14-15, Phillips teaches the die of claim 1, wherein:
a third set of circuit elements receives a third lithographic deposition of a second layer as the second layer is deposited to the first region using a third reticle of a third pattern aligned with the first region; and
a fourth set of circuit elements receives a fourth lithographic deposition of the second layer as the second layer is deposited to the second region using a fourth reticle of a fourth pattern aligned to the second region (See fig. 1B, Para 41).
As per Claims 9 and 16, Phillips teaches the die of claim 1, wherein the overlap region includes a plurality of rows of a grid or a plurality of columns of the grid (See fig. 6A-6B, Para 72-75).
As per Claim 10, Phillips teaches the die of claim 1, wherein the first reticle and the second reticle are arranged in an ordered pattern in the overlap region (See fig. 6A-6B, Para 72-75).
As per Claims 11 and 17, Phillips teaches the die of claim 1, wherein the first reticle and the second reticle are arranged in a randomized pattern in the overlap region (See fig. 6A-6B, Para 72-75).
As per Claim 18, Phillips teaches a set of reticles (See fig. 1A, Para 39-40) including:
a first reticle (108 R1) of a first pattern A configured to be aligned with a first region of a die for a first lithographic deposition of a first layer to a first set of circuit elements of an array of circuit of elements in an overlap region, the die being fabricated to include the array of circuit elements arranged in a grid spanning the first region and a second region that overlap in the overlap region (Para 72); and
a second reticle (109 R2) of a second pattern B configured to be aligned with the second region of the die for a second lithographic deposition of the first layer to a second set of circuit elements of the array of circuit elements in the overlap region, the first lithographic deposition and the second lithographic deposition do not overlap on a same circuit element in the overlap region (See fig. 6A-6B, Para 72-75).
As per Claim 20, Phillips teaches the set of reticles of claim 18, wherein: the overlap region includes a plurality of rows of a grid or a plurality of columns of the grid; and the first reticle and the second reticle are arranged in a randomized pattern in the overlap region (See fig. 6A-6B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Phillips.
As per Claims 2-3, 13 and 19, Phillips teaches the die of claim 1.
Phillips does not explicitly disclosed wherein the array of circuit elements includes an array of pixels and the die is implemented as an image sensor die configured to produce a photographic image based on light detected by the array of pixels.
Phillips further disclosed a device layer of substrate 201 may include any devices such as transistors, memory devices, capacitors, resistors, optoelectronic devices, switches, or any other active or passive electronic devices. Such devices are fabricated using known techniques such as lithography, etch, deposition, implant, etc. Dielectric layer 1002 is over substrate 201. For example, substrate 201 may include metallization layers at a top thereof that are to be contacted by reticle stitched metal lines formed in dielectric layer 1002 using single damascene or dual damascene techniques (Para 88-91, wherein the claimed devices are abundantly produced in the art).
Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate the arrangement of circuit elements as claimed in order to produce a desired device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MESFIN ASFAW whose telephone number is (571)270-5247. The examiner can normally be reached Monday - Friday 8 am - 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toan Ton can be reached at 571-272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MESFIN T ASFAW/ Primary Examiner, Art Unit 2882
Prosecution Insights