DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Burton et al. [US 20200066651 A1, hereafter Burton].
As per Claims 1 and 12, Burton teaches a die 104 (See fig. 1, Para 25, a maximum number semiconducting die that can be fit onto a surface of the substrate) comprising:
a first region (a first reticle field 402) and a second region (a second reticle field 410) that overlap in an overlap region (the reticle field overlap 416) (See fig. 4B, Para 64);
an array of circuit elements arranged in a grid spanning the first region and the second region (See fig. 1, Para 16, fabricating integrated circuit devices that span multiple reticle fields); and
an overlap set of circuit elements including circuit elements from the array that are disposed in the overlap region (Para 15, the overlapping conductive interconnections extend into a common scribe zone between adjacent reticle fields), wherein:
a first subset of the overlap set receives a lithographic deposition of a first layer as the first layer is deposited to the first region using a first reticle aligned with the first region (See fig. 4, Para 64, patterning 404 a photolithographic layer of an integrated circuit device within a first reticle field 402 using a reticle), and
a second subset of the overlap set receives the lithographic deposition of the first layer as the first layer is deposited to the second region using a second reticle aligned with the second region (patterned 412 in a second reticle field 410 adjacent to and overlapping with the first reticle field 402).
As per Claims 2 and 13, Burton teaches the die of claim 1, wherein the array of circuit elements includes an array of pixels and the die is implemented as an image sensor die configured to produce a photographic image based on light detected by the array of pixels (Para 32, wherein field effect transistors (FETs), finFETs, planar FETs, MOSFETs, as well as many other types of semiconductor devices).
As per Claim 3, Burton teaches the die of claim 2, wherein the array of circuit elements further includes a plurality of access circuits corresponding to the array of pixels and configured to facilitate operation of the array of pixels during production of the photographic image (Para 32, wherein field effect transistors (FETs), finFETs, planar FETs, MOSFETs, as well as many other types of semiconductor devices).
As per Claims 4 and 14, Burton teaches the die of claim 1, wherein: a third subset of the overlap set receives a lithographic deposition of a second layer as the second layer is deposited to the first region using a third reticle aligned with the first region; and a fourth subset of the overlap set within the overlap set receives the lithographic deposition of the second layer as the second layer is deposited to the second region using a fourth reticle aligned to the second region (See fig. 2A).
As per Claim 5, Burton teaches the die of claim 4, wherein: the third subset is different from the first subset and the second subset; the first layer is of a first layer type selected from a group consisting of a metal layer type, a doping layer type, and a dielectric layer type; and the second layer is of a second layer type selected from the group and different from the first layer type (Para 26-30, each of the individual reticle fields 108A-108D is separated from adjacent reticle fields by a scribe zone).
As per Claim 6, Burton teaches the die of claim 1, wherein the die further comprises: a third region that overlaps the second region in an additional overlap region and that is also spanned by the grid; and an additional overlap set of circuit elements including circuit elements from the array that are disposed in the additional overlap region, wherein: a third subset of the additional overlap set receives the lithographic deposition of the first layer as the first layer is deposited to the second region using the second reticle aligned with the second region, and a fourth subset of the additional overlap set receives the lithographic deposition of the first layer as the first layer is deposited to the third region using a third reticle aligned with the third region (See fig. 2A, Para 26-30).
As per Claim 7, Burton teaches the die of claim 6, wherein the first region, the second region, and the third region are arranged collinearly such that the second region is disposed between the first region and the third region (See fig. 3C).
As per Claim 8, Burton teaches the die of claim 6, wherein: the third region is arranged non-collinearly with the first region and the second region; and the overlap region and the additional overlap region overlap in a hyper-overlap region that includes: a first circuit element that receives the lithographic deposition of the first layer as the first layer is deposited to the first region using the first reticle aligned with the first region, a second circuit element that receives the lithographic deposition of the first layer as the first layer is deposited to the second region using the second reticle aligned with the second region, and a third circuit element that receives the lithographic deposition of the first layer as the first layer is deposited to the third region using the third reticle aligned with the third region (See fig. 2A, Para 26-30).
As per Claims 9 and 16, Burton teaches the die of claim 1, wherein the overlap region includes a plurality of rows of the grid or a plurality of columns of the grid (See fig. 1).
As per Claim 10, Burton teaches the die of claim 1, wherein the overlap set of circuit elements is divided into the first subset and the second subset in accordance with an ordered pattern (See fig. 2A).
As per Claim 11, Burton teaches the die of claim 1, wherein the overlap set of circuit elements is divided into the first subset and the second subset in accordance with a randomized pattern (See fig. 4B).
As per Claim 15, Burton teaches the method of claim 12, further comprising performing, while a third reticle is aligned with a third region of the die that overlaps the second region in an additional overlap region in which is disposed an additional overlap set of circuit elements from the array, the lithographic deposition of the first layer on the third region; wherein: the performing of the lithographic deposition of the first layer on the second region includes depositing the first layer to a third subset of the additional overlap set, and the performing of the lithographic deposition of the first layer on the third region includes depositing the first layer to a fourth subset of the additional overlap set (See fig. 2A, Para 26-30).
As per Claim 17, Burton teaches the method of claim 12, wherein the overlap set of circuit elements is divided into the first subset and the second subset in accordance with a randomized pattern (Para 32).
As per Claim 18, Burton teaches a set of reticles configured for use in a lithographic deposition of a first layer on a die being fabricated to include an array of circuit elements arranged in a grid (Para 18, Multi-reticle die of the present disclosure can be fabricated by overlapping a first reticle field with a second reticle field so that the first reticle field and the second reticle field have a common scribe zone), the set of reticles including:
a first reticle configured to be aligned with a first region of the die (a first reticle field 402) for the lithographic deposition of the first layer on the first region; and a second reticle configured to be aligned with a second region of the die (a second reticle field 410) for the lithographic deposition of the first layer on the second region (See fig. 4B, Para 64);
wherein:
the first region overlaps the second region in an overlap region in which is disposed an overlap set of circuit elements from the array,
the first reticle is configured for use in the lithographic deposition of the first layer to a first subset of the overlap set, and the second reticle is configured for use in the lithographic deposition of the first layer to a second subset of the overlap set (Para 15, the overlapping conductive interconnections extend into a common scribe zone between adjacent reticle fields).
As per Claim 19, Burton teaches the set of reticles of claim 18, wherein the array of circuit elements includes an array of pixels and the die being fabricated implements an image sensor die configured to produce a photographic image based on light detected by the array of pixels (Para 32, wherein field effect transistors (FETs), finFETs, planar FETs, MOSFETs, as well as many other types of semiconductor devices).
As per Claim 20, Burton teaches the set of reticles of claim 18, wherein: the overlap region includes a plurality of rows of the grid or a plurality of columns of the grid; and the overlap set of circuit elements is divided into the first subset and the second subset in accordance with a randomized pattern (See fig. 1).
Claim(s) 1, 12 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. [US 20190164899 A1, hereafter Hu].
As per Claims 1, 12 and 18, Hu teaches a die (See fig. 1, die 100) comprising:
a first region 110A and a second region 110B that overlap in an overlap region 110AB;
an array of circuit elements arranged in a grid spanning the first region and the second region (See fig. 1); and
an overlap set of circuit elements including circuit elements from the array that are disposed in the overlap region (Para 12), wherein:
a first subset of the overlap set receives a lithographic deposition of a first layer as the first layer is deposited to the first region using a first reticle aligned with the first region, and a second subset of the overlap set receives the lithographic deposition of the first layer as the first layer is deposited to the second region using a second reticle aligned with the second region (Para 15-16).
Conclusion
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/MESFIN T ASFAW/ Primary Examiner, Art Unit 2882