Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Claim(s) 1-9, 21-31 in the reply filed on 8/24/2026 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 21-26, 28-31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xia et al. (CN 203983270).
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CLAIM 1. Xia teaches a chip stack, comprising: a plurality of stacked chips including a first chip and a second chip adjacent to the first chip, each of the first chip and the second chip having an active side (“front face” “front circuit layer” indicates front side is active. ¶6)1 and a passive side 8 opposite the active side (mirco channels are “back etched” indicating they are formed in the back side.), the active side of the first chip facing and bonded to the passive side of the second chip, the passive side of the second chip having at least one cavity 8, and a portion of the active side of the first chip covering the at least one cavity to define at least one first microchannel between the first chip and the second chip (Fig. 7 & Claim 3)2.
CLAIM 2. Xia teaches a chip stack of claim 1, wherein the plurality of stacked chips further includes a third chip adjacent to the second chip, the active side of the second chip facing the passive side of the third chip, the passive side of the third chip having at least one cavity covered by the active side of the second chip to define at least one second microchannel, the at least one second microchannel being fluidly coupled to the at least one first microchannel (Fig. 7 & ¶6).
CLAIM 3. Xia teaches a chip stack of claim 2, wherein the second chip includes a fluid through hole extending from the at least one cavity on the passive side of the second chip to the active side of the second chip, and the at least one first microchannel is fluidly coupled to the at least one second microchannel through the fluid through hole (Fig. 7 & ¶6).
CLAIM 4. Xia teaches a chip stack of claim 2, wherein the at least one second microchannel has an outlet at a lateral edge of the third chip.
CLAIM 5. Xia teaches a chip stack of claim 1, wherein the passive side of the first chip has at least one cavity, the chip stack further comprising a top chip stacked over the first chip, an active side of the top chip covering the at least one cavity on the passive side of the first chip to define at least one further microchannel, the top chip including at least one through hole TSFV configured to inject a cooling fluid into the at least one further microchannel (Fig. 7 & ¶6).
CLAIM 6. Xia teaches a chip stack of claim 1, wherein the at least one cavity on the passive side of the second chip has a depth in a range of 10pm to 150pm, and a width in a range of 30pm to 200pm (Fig. 7 & ¶653)..
CLAIM 7. Xia teaches a chip stack of claim 1, wherein a cross section of the at least one cavity taken along a thickness direction of the second chip has a rectangular shape (Fig. 7).
CLAIM 8. Xia teaches a chip stack of claim 1, wherein each of the first chip and the second chip includes through vias TSEV extending between the active side and the passive side thereof, each of the through vias includes a conductive post, conductive posts in the through vias of the first chip are respectively bonded to conductive posts in the through vias of the second chip, and the through vias of the second chip are spaced apart from the at least one cavity in any direction along a surface of the passive side of the second chip (Fig. 7 & ¶6).
CLAIM 9. Xia teaches a chip stack of claim 1, wherein the plurality of stacked chips includes at least one of a high bandwidth memory chip or a system-on- chip (Fig. 7 – The limitation regarding the chip type is purely functional and imports no distinct structural characteristics into the claim.).
CLAIM 21. Xia teaches a chip stack of claim 8, wherein a shortest distance between the at least one cavity and any of the through vias of the second chip is equal to or greater than a shortest distance between two neighboring ones of the through vias of the second chip (Fig. 7).
CLAIM 22. Xia teaches a chip stack of claim 1, wherein the at least one first microchannel is configured to conduct a cooling fluid comprising water and/or ethylene glycol (Fig. 7 – “configured to” does not provide any clear distinction over using particular type of fluids.).
CLAIM 23. Xia teaches a chip stack of claim 1, wherein the active side of the first chip is hybrid bonded to the passive side of the second chip and contacts portions of the passive side of the second chip around a periphery of the at least one cavity (Fig. 7)..
CLAIM 24. Xia teaches a chip stack of claim 1, wherein the at least one cavity comprises a serpentine cavity extending across the passive side of the second chip, the serpentine cavity having an inlet at or near a first end thereof and an outlet at or near a second end thereof (Figs. 6b & 7).
CLAIM 25. Xia teaches a chip stack of claim 2, wherein an inlet of the at least one second microchannel overlaps, in a stacking direction of the plurality of stacked chips, an outlet of the at least one first microchannel (Figs. 6b & 7)..
CLAIM 26. Xia teaches a chip stack of claim 1, wherein a cross section of the at least one cavity taken along a thickness direction of the second chip has a trapezoidal shape or a semicircular shape (Figs. 6b & 7 – Under the Broadest Reasonable Interpretation (BRI) standard, the claimed "recess microcavity (14)" is structurally identical to, or at least reads directly upon, the microchannels disclosed in Xia. Applicant’s own specification depicts the recess microcavity (14) as a three-sided trench, which encompasses various geometric configurations. Because Xia discloses microchannels in the exact same manner, Xia's structure effectively reads on a "semicircle" to the same extent that Applicant's disclosure encompasses semicircular or trapezoidal cross-sections. Therefore, Xia’s disclosure fully satisfies this claim limitation.)
CLAIM 28. Xia teaches a chip stack, comprising: a stack of chips including a plurality of chips stacked in a stacking direction and a top chip stacked over the plurality of chips (Fig. 7 & ¶6), each chip of the stack of chips having an active side and a passive side opposite the active side (Fig. 7 & ¶6), the passive side of each chip of the plurality of chips being attached to the active side of a neighboring chip of the stack of chips and having at least one cavity that forms a microchannel with the active side of the neighboring chip(Fig. 7 & ¶6), wherein the microchannel on the passive side of each chip of the plurality of chips is fluidly coupled to the microchannel on the passive side of an adjacent chip of the plurality of chips such that a cooling fluid injected into an inlet of the microchannel on the passive side of an inlet chip of the plurality of chips flows successively through the microchannels on the passive sides of the plurality of chips before exiting via an outlet of the microchannel on the passive side of an exit chip of the plurality of chips (Fig. 7 & ¶6).
CLAIM 29. Xia teaches a chip stack of claim 28, wherein each chip of the plurality of chips other than the exit chip includes a fluid through hole TSFV extending from the at least one cavity on the passive side of the chip to the active side of the chip, the fluid through hole fluidly coupling the microchannel on the passive side of the chip to the microchannel on the passive side of an adjacent chip whose passive side faces the active side of the chip (Fig. 7 & ¶6).
CLAIM 30. Xia teaches a chip stack of claim 28, wherein the top chip is bonded to the passive side of the inlet chip of the plurality of chips, the top chip including at least one injection through hole fluidly coupled to the microchannel on the passive side of the inlet chip and configured for injection of the cooling fluid into the microchannel on the passive side of the inlet chip (Fig. 7 & ¶6).
CLAIM 31. Xia teaches a cooling system, comprising: the chip stack of claim 28; and a heat exchanger fluidly coupled between the outlet and the inlet, the heat exchanger configured to cool the cooling fluid discharged from the outlet before the cooling fluid is returned to the microchannel of the inlet chip (Fig. 7 &¶1-34 ¶6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xia et al. (CN 203983270 U)
CLAIM 27. Xia teaches a chip stack of claim 1, however may be silent upon wherein the plurality of stacked chips comprises at least sixteen chips. It would have been obvious to a person of ordinary skill in the art (PHOSITA) at the time of the invention to scale the plurality of stacked chips to comprise at least sixteen chips. In the art of semiconductor fabrication and integrated circuit design, the number of chips in a stack is a well-known result-effective variable.
Under established patent law, "the discovery of an optimum value of a result effective variable in a known process is ordinarily within the skill of the art." In re Antonie, 559 F.2d 1063, 195 USPQ 6 (CCPA 1977). A PHOSITA would recognize that the precise number of layers or chips in a semiconductor stack is a matter of routine optimization dictated by the specific engineering constraints of the target application, such as desired memory capacity, data bandwidth, and form factor limitations.
Increasing the number of chips to sixteen represents a predictable replication of known components to achieve a cumulative, expected result (i.e., increased processing power or data storage within a localized footprint). The applicant has not demonstrated that a 16-chip configuration yields any unexpected or synergistic results beyond what would be mathematically and physically predicted by simply scaling the stack. Therefore, the modification represents nothing more than routine design choice and scaling to achieve a desired, predictable result.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/22/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Xia - [0006] This utility model design a interlayer complex micro-channel liquid forced convection cooling for 3D-1C, wherein, as shown in FIG. 1, comprises a sealing sheet (I) sequentially stacked packaged together, a complex micro-channel chip layer (2.1, 2.2, 2.3), a connection layer (3), a sealing sheet (I) is provided with a fluid entrance (4) connected with an external pipeline, a fluid outlet (5), a core layer of complex micro-channel is divided into an upper core layer (2.1) with complex micro-channel. a middle core layer (2.2) of complex micro-channel, with bottom chip layer (2.3) with complex micro-channel, one surface of a surface defining the sealing sheet (I) is the back surface of the chip layer, away from the front face; with the complex micro-channel of the upper chip layer (2.1) back etching the complex micro-channel (8), a front circuit layer or microelectronic device ¢), complex micro-channel (8) left and right two sides are provided with TSFV through hole (7), the TSFV through hole (7) communicated with the complex micro-channel of the upper chip layer (2.1); the upper chip layer (2.1) there is no need to TSEV (9), with the complex micro-channel of the middle core layer (2.2) back etching the complex micro-channel (8), a front circuit layer or microelectronic device ¢), complex micro-channel (8) left and right two sides provided with a TSFV through hole (7). TSFV through hole (7) communicated with the complex micro-channel of the middle core layer (2.2), the rib of the complex micro-channel (8) is set with joint and lower layer of silicon through hole electrically connected with the TSEV (9), with bottom chip layer (2.3) is etched with complex micro-channel complex micro-channel (8); the front circuit layer or microelectronic components), complex micro-channel (8) left and right two sides are provided with TSFV (7), TSFV (7) is connected with the complex micro-channel bottom chip layer (2.3); complex micro-channel (8) is provided with a connected with the upper electric silicon via electrically connected with the TSEV (9), because the chip layer on the 3D chip of the bottom layer, in order to form the sealed chamber of the fluid flow and the etching depth TSFV of the layer chip (7) and the depth of the micro-channel (8) are the same; TSFV (7) so as to form sealed bottom.
2 Claim 3: 3. The method according to claim 1 with an interlayer complex micro-channel liquid forced convection cooling for 3D-1C, wherein the complex microchannel is composed of strip microstructure containing sector groove or the long micro-structure with triangular grooves staggered to form a channel; the fan-shaped groove of the strip microstructure is based to a plurality of parallel straight strip structure, any one straight strip and the adjacent flat strip parallel and opposite two side faces are carved with fan-shaped groove, the groove is concave flat strip centre shaft; the level height of the height with straight strip of fan-shaped groove, groove height where the fan is parallel with the central axis of the flat strip, fan-shaped grooves at two side straight long side staggered uniformly dispersedly arranged, namely at the same side is fan-shaped groove and straight plane has not been etched are distributed alternately. the same straight long two sides of fan-shaped groove is staggered, namely, sector groove corresponding to one side of straight plane and the other side surface of the un-etched, forming an undulating shape when viewed from the overall; between any adjacent two of strip microstructure containing sector groove structure to form the opposite two sides of the micro-channel is sector groove opposite fan-shaped groove; the straight plane straight plane has not been etched is not etched, long micro-structure containing the triangular groove of the strip microstructure with sector groove are the same, only replacing the fan-shaped groove is triangular groove.
3 Xia - [0065] height of staggered triangular concave micro-channel is 200, the distance is 200 microns. an enlarged view of the single channel shown in FIG. 6, the staggered two right-angle sides of concave micro-channel with the linear form length triangular rib structure that the side wall is composed of right angle side is 0.1 mm of the isosceles right-angled triangle of 0.2 mm unit, two side wall of the rib structure in staggered structure. the minimum width of the staggered triangular recess micro-channel rib is 50 microns. triangular recess micro-staggered passage at two triangular recess formed in the middle of the maximal space is 200 microns; the two straight middle form the smallest distance is 100 microns.
4 Xia - [0001] This utility model belongs to 3D-1C microelectronic heat dissipation technology field, relating to a micro-cooling structure, especially the complex micro-channel can effectively take away the heat of the chip, and realize relatively uniform temperature distribution. and tungsten or tungsten bronze is used as the TSEV material, with good thermal conductivity of doped inorganic nanoparticles (such as Si02, Ti02, Al203, AlN, C, etc.) of the polyimide composite film as connection layer of fill material enhances the heterogeneous material and enhance the heat exchange.
BACKGROUND-ART
Background technology
[0002] the recent years, the integrated technology of 3D-1C (integrated circuit), a frame design, cost analysis, temperature control, route planning, and reliability analysis more research and so on. With the continuous improvement of ultra-large scale integrated circuit development and application requirements, two-dimensional chip which can not satisfy the requirement, and has low power consumption, short transmission distance, and fast transfer rate, low delay, low noise, fuel-leaking 3D-1C becomes the attractive focus. TVS (silicon through-hole) and CM0S (complementary metal oxide semiconductor) realizes electric connection 3D-1C vertical direction to realize the real meaning of 3D-1C. However, since the stack the chip power consumption density of integrated circuit caused by increasing the chip increases exponentially on the same area, and connected with the insulating dielectric layer of interlayer low conductivity of the circuit, the traditional cooling mode and applied to two-dimensional chip micro-channel heat sink which can not effectively take away heat of the chip. heat the chip accumulation will cause the temperature of the chip rises, uneven temperature distribution of the chip, the serious influence the working state of chip and stability, even to damage the chip due to thermal stress. Therefore, 3D-1C heat dissipation technology important efficiently and stably.
[0003] abroad 3D-1C heat analysis mainly from two aspects of research: (I) the reasonable layout function module, the balance between module power consumption density prevents the over-hot circuit failure, (2) strengthening heat exchange to the chips and the heat of the chip is transmitted to the external environment. However, depending on mole theorem as the height of chip power consumption density of integrated 3D-1C rapidly increases, even through rational layout function module, highest temperature of the chip will also reach 150 degrees centigrade. the reinforced heat exchange of 3D-1C mainly has two forms: (I) external heat transfer enhancement device, such as fan with forced heat convection type radiator, back adhesive sink (micro-channel heat sink) reinforced heat exchange, (2) 3D chip interlayer cooling, such as heat conducting through hole formed by TVS chip transfer layer between the micro-channel structure is formed between the circuit layers by etching technology and for forced convection heat away the chip. Although the optimized external strengthening heat exchange device with good heat exchange performance, but the multilayer stack 3D-1C, it does not directly contact with the heat exchange device of the heat generated by the circuit layer is hard to radiate, produce much more serious heat hazard, is continuously accumulated heat will seriously damage the performance of the chip and may even cause chip failure. thermal through holes has a thermal conductivity higher than the medium insulating layer between the device layer and the chip, between the chip layer inserted with heat through hole which is good for the heat emitted from the device of the upper layer chip is conducted downwards. However, if between the chip into a plurality of thermal through holes will cause chip reliability is reduced, besides inserting too much heat through hole wiring resources is reduced. layer between the fluid cooling with good heat exchanging effect of cooling is considered to be 3D-1C of the most promising and most effective method.
Prosecution Insights