DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I and Species B encompassing claims 1-4 and 6-10 in the reply filed on August 10, 2026 is acknowledged. The traversal is on the ground(s) that there must be a search burden for examination to be proper.
Regarding the restriction between Inventions I and II, since Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement between Inventions I and II, the election of Invention I has been treated as an election without traverse (MPEP § 818.01(a)).
With regard to the restriction between Species A and Species B, Applicant’s arguments are persuasive in that there is no serious search and/or examination burden for searching Species A in addition to Species B. Accordingly, the restriction between Species A and Species B is withdrawn.
With regard to the restriction between Species A, B and Species C, while Applicant argues that generic claim 1 encompasses the features of Species A, B, and C, this is not found persuasive because there is an undue search burden as specific keyword searches would need to be conducted to search for the mutually exclusive features of the different species as in Species A and B, the bottom surface of the first bonding material 291 is positioned above the carrier structure 24/34 while in Species C, the first bonding material 291 is positioned in a groove 440 of the carrier structure 44, and therefore the bottom surface of the first bonding material 291 is not positioned above the carrier structure 44 as outlined in the Restriction Requirement mailed on August 10, 2026. Accordingly, the restriction between Species A, B and Species C is maintained.
Therefore, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 includes “an electronic structure tightly bonded to the carrier structure via a bonding layer,” and the terminology “tightly” is a relative term which renders the claim indefinite. The term “tightly” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purposes of examination, the above limitation will be interpreted as “an electronic structure bonded to the carrier structure via a bonding layer.”
Claim 1 includes “a first bonding material and a second bonding material adjacent to the first bonding material to form a non-parallel double-layer structure” and it is unclear if this means the double-layer structure has a surface that is non-parallel to a surface of another structure or if this means one of the layers of the double-layer structure has a surface that is non-parallel to a surface of another one of the layers of the double-layer structure. For the purposes of examination, the above limitation will be interpreted as “a first bonding material and a second bonding material adjacent to the first bonding material to form a double-layer structure where a surface of the first bonding material is non-parallel to a surface of the second bonding material.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s)s 1-4, 6, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20220148975A1 (“Chen”) in view of US20020031868A1 (“Capote”).
RE: Claim 1, Chen discloses An electronic package (2 in FIG. 2G), comprising:
a carrier structure (20, [0055]);
an electronic structure (2b or 21, which is included in 2b in FIG. 2G; 21 is a semiconductor chip, [0037]) tightly bonded to the carrier structure via a bonding layer (24 labeled in FIG. 2G, [0036]), wherein the bonding layer comprises a first bonding material (24 can be a paste such as a non-conductive film, [0040]);
a plurality of conductive pillars (23, [0041]) disposed on and electrically connected to the carrier structure;
an encapsulating layer (25, [0046]) formed on the carrier structure and covering the electronic structure and the plurality of conductive pillars; and
a circuit structure (26, [0050]) disposed on the encapsulating layer and electrically connected to the electronic structure and the plurality of conductive pillars.
Chen does not explicitly disclose:
the bonding layer comprises a second bonding material adjacent to the first bonding material to form a non-parallel double-layer structure.
In the same field of endeavor, Capote discloses in FIG. 12:
a bonding layer (110, 112, [0085]) comprises a first bonding material (112) and a second bonding material (110) adjacent to the first bonding material to form a non-parallel double-layer structure (FIG. 12 shows 110, 112 form a double-layer structure where the leftmost upper surface of 110 is non-parallel to the upper surface of 112).
Capote further discloses the encapsulants 110 and 112 provide a continuous seal between the chip 100 and the substrate 101 completely engulfing the solder interconnections 102, [0085].
Capote further discloses The present invention also provides chips with underfilling encapsulants pre-coated and pre-assembled on the chips for assembly to a substrate, wherein the encapsulant consists of more than one layer or portion, each portion performing one or more distinct functions such as adhesion, stress reduction, electrical redistribution, reworkability, or other functions, [0093].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the bonding layer 24 to include a first bonding material and second bonding material forming non-parallel surfaces as taught by Capote in order to provide a continuous seal between the chip 21 and the substrate 20 engulfing conductive bumps 22 and/or to reduce stress as further taught by Capote.
RE: Claim 2, Chen in view of Capote discloses The electronic package of claim 1, wherein the carrier structure comprises a dielectric layer (From Chen: 200’ in FIG. 2G, [0055]) and a wiring layer (From Chen: 201 labeled in FIG. 2F, [0055]) bonded to the dielectric layer, and the wiring layer is electrically connected to the electronic structure (Chen FIG. 2F shows 201 electrically connected to bumps 22 which are electrically connected to 21 as shown in FIGs. 2A-2B).
RE: Claim 3, Chen in view of Capote discloses The electronic package of claim 1, wherein the electronic structure has a plurality of conductive bumps (22 in Chen FIG. 2G, [0045]) embedded in the bonding layer, and a plurality of openings (openings occupied by 201 in 200’ as shown in Chen FIG. 2F) corresponding to the plurality of conductive bumps are formed on the carrier structure (20 or 203 which is part of 20).
RE: Claim 4, Chen in view of Capote discloses The electronic package of claim 3, further comprising a wiring layer (From Chen FIG. 2F: 201, [0055]) formed in the plurality of openings and electrically connected to the plurality of conductive bumps (Chen FIG. 2F shows 201 electrically connected to 22 labeled in FIG. 2G).
RE: Claim 6, Chen in view of Capote discloses The electronic package of claim 1, wherein the electronic structure is electrically connected to the circuit structure via a plurality of conductive bumps (280b in Chen FIG. 2G; Chen teaches 280b are copper pillars, [0039]; conductive bumps can be copper pillars, [0042]; Accordingly, copper pillars 280b are considered conductive bumps).
RE: Claim 9, Chen in view of Capote discloses The electronic package of claim 1, further comprising at least one electronic element (29 in Chen FIG. 2G, [0054]) disposed on and electrically connected to the circuit structure.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Capote as applied to claim 1, further in view of US20220415842A1 (“Ko”).
RE: Claim 7, Chen in view of Capote does not explicitly disclose The electronic package of claim 1, wherein the first bonding material is a non-conductive film.
However, Capote discloses The major encapsulant portion 111 comprises a liquid polymer resin that is filled with inorganic powder, [0083].
Capote further discloses the assembly is then heated preferably using convection reflow technology to cure the liquid encapsulants to form encapsulants 110 and 112, [0085].Capote further discloses The thermal expansion coefficients and elastic moduli of the resins can be reduced by the addition of inorganic fillers, such as silica, [0010].
In the same field of endeavor, Ko discloses:
Each of the plurality of non-conductive films (NCFs) 88 may include a resin and a filler. The filler may include silica, [0034].
Ko further discloses A selected one of the plurality of non-conductive films (NCFs) 88 may be bonded between the first semiconductor chip 30 and the first substrate 20, [0035].
FIG. 1 shows each non conductive film 88 surrounds a plurality of conductive bumps 77, [0034].
Accordingly, as modified, Capote’s first bonding material / encapsulant 112 is a cured resin filled with an inorganic silica powder, which in view of Ko, would correspond to the claimed non-conductive film.
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute Capote’s first bonding material / encapsulant 112 with a non-conductive film since both are taught by Capote, Ko as materials used to surround conductive bumps and the results of the substitution would have been predictable, see MPEP 2143.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Capote as applied to claim 1, further in view of US20160247767A1 (“Kim”).
RE: Claim 8, Chen in view of Capote does not explicitly disclose The electronic package of claim 1, wherein the second bonding material is a non-conductive paste.
However, Chen discloses 22 are solder balls, [0042].
Further, Capote discloses One advantage of this technique is that the reflow and underfilling steps are combined into one, thereby eliminating the slow underfill operation since the encapsulating underfill is applied prior to assembly, [0018].
Capote further discloses 109 is a polymer flux, [0017].
Capote discloses that 109 cures to form the encapsulant 110 in FIG. 12, [0085].
FIGs. 11-12 show the solder bumps 108 forming solder interconnections 102, [0085].
In the same field of endeavor, Kim discloses in FIG. 2I:
The underfill 340 is positioned between the semiconductor die 310 and the interposer 100, for example surrounding lateral surfaces of the bond pads 320, solder bumps 330, [0049].
Kim discloses block 1130 may comprise underfilling the semiconductor die utilizing a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape while the die are being attached at block 1130 (e.g., utilizing a thermocompression bonding process). For example, such underfill materials may be deposited (e.g., printed, sprayed, etc.) prior to attaching the semiconductor die (e.g., as a pre-applied underfill). The underfill may comprise any of a variety of types of material, for example, an epoxy, a thermoplastic material, a thermally curable material, polyimide, polyurethane, a polymeric material, filled epoxy, a filled thermoplastic material, a filled thermally curable material, filled polyimide, filled polyurethane, a filled polymeric material, a fluxing underfill, and equivalents thereof, [0047].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute Capote’s second bonding material / encapsulant 110 with a non-conductive paste as both are taught as being pre-applied fluxing underfills used to surround solder bumps, and the results of the substitution would have been predictable, see MPEP 2143.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Capote as applied to claim 1, further in view of US20230136541A1 (“Lin”).
RE: Claim 10, Chen in view of Capote does not explicitly disclose The electronic package of claim 1, further comprising a plurality of electronic elements disposed on and electrically connected to the circuit structure, wherein the electronic structure electrically bridges at least two of the plurality of electronic elements.
However, in the embodiment of FIG. 2G’, Chen discloses electronic structure 2 b acts as an electrical bridge component between the at least two electronic components 29, 29’, [0063].
Further, Chen discloses 29 is at least one electronic component, [0054].
In the same field of endeavor, Lin discloses in FIG. 2H:
a plurality of electronic elements (26, [0063]) disposed on and electrically connected to a circuit structure (20, [0063]), wherein an electronic structure (2a) electrically bridges at least two of the plurality of electronic elements (the electronic structure 2 a is used as a bridge die, which is electrically connected to the circuit structure 20 via the first conductors 21 a, and electrically bridges at least two electronic components 26, [0064]).
Lin further discloses As a result, the method for manufacturing an electronic package according to the present disclosure uses the electronic structure 2 a as a bridge die to directly electrically conduct at least two upper active chips (i.e., the electronic components 26) such that the electrical path is shortened, and the pitch between I/O pins or between electrical contact pads 202 can be effectively reduced as required. Besides, the number of layers of the RDLs 201 for electrical connection between upper and lower layers of the circuit structure 20 can also be reduced to increase the process yield, [0080].
Lin further discloses Consequently, the electrical paths can be shortened, and the electrical performance can be improved, [0081].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of electronic components on the circuit structure 26 using the electronic structure 2b to electrically bridge the electronic components as taught by Lin in order to shorten electrical paths and improve electrical performance as further taught by Lin.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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