DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2, claims 1-20 in the reply filed on September 23, 2026 is acknowledged. Action on the merits is as follows:
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2, 4, 7, 10, 12, 14, 17, 19 and 20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 4, 7 and 18-20 of U.S. Patent No. 11,404,534 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
In regards to claim 1, 11,404,534 B2 (claim 1) discloses a structure comprising: a semiconductor substrate having a frontside surface and a backside surface; a well region extending into the frontside surface and corresponding to an active semiconductor device; a frontside interconnect structure disposed beneath the frontside surface; and a trench disposed in the backside surface of the semiconductor substrate, the trench including a first capacitor electrode corresponding to a doped semiconductor region along sidewalls and a lower surface of the trench, a capacitor dielectric layer in the trench and overlying the first capacitor electrode, and a second capacitor electrode in the trench and overlying the capacitor dielectric layer; wherein a line parallel to the frontside and backside surfaces of the semiconductor substrate intersects both the well region and the doped semiconductor region corresponding to the first capacitor electrode.
In regards to claim 2, 11,404,534 B2 (claim 1) discloses wherein the semiconductor substrate has a reduced thickness as measured from a bottom surface of the trench to the frontside surface, and wherein the reduced thickness is less than an overall thickness of the semiconductor substrate as measured from the frontside surface to the backside surface and is less than a depth of the well region.
In regards to claim 4, 11,404,534 B2 (claims 4, 19) discloses further comprising: a third capacitor electrode in the trench and spaced apart from the second capacitor electrode by a second capacitor dielectric layer.
In regards to claim 7, 11,404,534 B2 (claims 4, 19) discloses further comprising: an intermediate capacitor electrode disposed in the trench between the first capacitor electrode and the second capacitor electrode.
In regards to claim 10, 11,404,534 B2 (claims 4, 19) discloses A structure comprising: a semiconductor substrate having a frontside surface and a backside surface; a frontside interconnect structure disposed beneath the frontside surface; and a trench disposed in the backside surface of the semiconductor substrate, the trench including a first capacitor electrode in a lower portion of the trench, a capacitor dielectric layer in the trench and overlying the first capacitor electrode, and a second capacitor electrode in the trench and overlying the capacitor dielectric layer; wherein the first capacitor electrode has lower outer corners where a bottom surface of the trench meets sidewalls of the trench and has upper inner corners above the trench, and wherein the first capacitor electrode has a sidewall region extending continuously from the lower outer corners to the upper inner corners, the lower outer corners being rounded and the upper inner corners being square.
In regards to claim 12, 11,404,534 B2 (claims 3, 18) discloses further comprising: a doped semiconductor region lining sidewalls of the trench and a bottom surface of the trench, the doped semiconductor region coupled to the first or second capacitor electrode.
In regards to claim 14, 11,404,534 B2 (claims 1 and 20) discloses wherein the semiconductor substrate has a reduced thickness as measured from a bottom surface of the trench to the frontside surface, and the reduced thickness being less than an overall thickness of the semiconductor substrate and being less than a depth of the well region.
In regards to claim 17, 11,404,534 B2 (claims 3, 18) discloses further comprising: a doped semiconductor region lining sidewalls of the trench and a bottom surface of the trench, the doped semiconductor region coupled to the first or second capacitor electrode.
In regards to claim 19, 11,404,534 B2 (claims 1 and 20) discloses wherein the semiconductor substrate has a reduced thickness as measured from a bottom surface of the trench to the frontside surface, and the reduced thickness being less than an overall thickness of the semiconductor substrate and being less than a depth of the well region.
In regards to claim 20, 11,404,534 B2 (claim 7) discloses wherein the semiconductor substrate includes monocrystalline silicon, and the trench is spaced apart from the well region solely by a portion of the monocrystalline silicon.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-9 is/are rejected under 35 U.S.C. 103 as being obvious over Clevenger et al. (Clevenger) (US 2007/0278619 A1) in view of Chang et al. (Chang) (US 2020/0176552 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
In regards to claim 1, Clevenger (Figs. 2A, 3A-3O and associated text) discloses a structure (Figs. 2A, 3O) comprising: a semiconductor substrate (item 110c) having a frontside surface (top surface of item 110c) and a backside surface (bottom surface of item 110c); a frontside interconnect structure (items 110b plus 110a plus 125 plus 130) disposed beneath the frontside surface (top surface of item 110c); and a trench (item 210) disposed in the backside surface of the semiconductor substrate (item 110c), the trench (item 210) including a first capacitor electrode (item 221), a capacitor dielectric layer (item 225) in the trench (item 210) and overlying the first capacitor electrode (item 221), and a second capacitor electrode (item 251) in the trench (item 210) and overlying the capacitor dielectric layer (item 225); but does not specifically disclose a well region extending into the frontside surface and corresponding to an active semiconductor device; …the trench including a first capacitor electrode corresponding to a doped semiconductor region along sidewalls and a lower surface of the trench, wherein a line parallel to the frontside and backside surfaces of the semiconductor substrate intersects both the well region and the doped semiconductor region corresponding to the first capacitor electrode.
Chang (Fig. 10 and associated text) discloses a well region (where item 1004 resides) extending into the frontside surface and corresponding to an active semiconductor device (item 1004); a trench (item 104t) including a first capacitor electrode (item 114) corresponding to a doped semiconductor region (item 104w) along sidewalls and a lower surface of the trench, a capacitor dielectric layer (item 112) in the trench (item 104t) and overlying the first capacitor electrode (item 114), and a second capacitor electrode (item 114) in the trench (item 104t) and overlying the capacitor dielectric layer (item 112); wherein a line parallel to the frontside and backside surfaces of the semiconductor substrate (item 104) intersects both the well region (where item 1004 resides, transistor) and the doped semiconductor region (item 104w) corresponding to the first capacitor electrode (item 114).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chang for the purpose of having a trench capacitor electrically coupled to a transistor.
In regards to claim 3, Clevenger as modified by Chang (Fig. 2B, 10 and associated text) discloses wherein the second capacitor electrode (item 114) has lowermost outer corners closest to where a bottom surface of the trench (item 104t) meets sidewalls of the trench (item 104t) and has upper inner corners above an uppermost surface of the trench (item 104t), and wherein the second capacitor electrode (item 114) has a sidewall region extending continuously from the lowermost outer corners to the upper inner corners, the lowermost outer corners being rounded and the upper inner corners being square.
It would have been obvious to modify the invention to include a second capacitor electrode having lowermost outer corners being rounded and the upper inner corners being square, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 4, Clevenger as modified by Chang (Fig. 2B, 10 and associated text) discloses further comprising: a third capacitor electrode (item 114) in the trench (item 104t) and spaced apart from the second capacitor electrode (item 114) by a second capacitor dielectric layer (item 112).
In regards to claim 5, Clevenger as modified by Chang (Fig. 2B, 10 and associated text) discloses further comprising: a backside interconnect structure (item 1006) disposed over the backside surface, the backside interconnect structure (item 1006) including a metal line (item 304) over the backside surface, wherein the second and third capacitor electrodes (item 114) each have a collar that extends upward beyond an upper surface of the trench, the collar of the second capacitor electrode (item 114) having an upper surface that lies along a first plane that intersects the metal line (item 3044) and the collar of the third capacitor electrode (item 114) having a lower surface that lies along a second plane lies that also intersects the metal line (item 304).
In regards to claim 6, Clevenger as modified by Chang (Fig. 2B, 10 and associated text) discloses wherein the second capacitor dielectric layer (item 112) encapsulates an upper surface, lower surface, and sidewalls of the second capacitor electrode (item 114).
In regards to claim 7, Clevenger as modified by Chang (Fig. 2B, 10 and associated text) discloses further comprising: an intermediate capacitor electrode (item 114) disposed in the trench (item 104t) between the first capacitor electrode (item 114) and the second capacitor electrode (item 114).
In regards to claim 8, Clevenger as modified by Chang (Fig. 2B, 10 and associated text) discloses further comprising: a backside interconnect structure (item 1006) disposed over the backside surface, the backside interconnect structure (item 1006) including a metal line (item 304) over the backside surface, wherein at least one of the second capacitor electrode (item 114) or the intermediate capacitor electrode (item 114) have an outermost surface that is nearer to the backside surface of the semiconductor substrate (item 104) than an upper surface of the metal line (item 304).
In regards to claim 9, Clevenger as modified by Chang (Fig. 2B, 10 and associated text) discloses wherein the doped semiconductor region (item 104w) has a constant depth as measured perpendicular to a bottom surface and sidewalls of the trench, and wherein the doped semiconductor region (item 104w) extends laterally along the backside surface of the semiconductor substrate (item 104) with the constant depth.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claim(s) 10-12 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clevenger et al. (Clevenger) (US 2007/0278619 A1) in view of TSUI et al. (TSUI) (US 2017/0271436 A1).
In regards to claim 10, Clevenger (Figs. 2A, 3A-3O and associated text) discloses a structure (Figs. 2A, 3O) comprising: a semiconductor substrate (item 110c) having a frontside surface (top surface of 110c) and a backside surface (bottom surface of item 110c); a frontside interconnect structure (items 110b pus 110a plus 125 plus 130) disposed beneath the frontside surface (top surface of 110c); and a trench (item 210) disposed in the backside surface of the semiconductor substrate (item 10c), the trench (item 210) including a first capacitor electrode (item 221) in a lower portion of the trench (item 210), a capacitor dielectric layer (item 225) in the trench and overlying the first capacitor electrode (item 221), and a second capacitor electrode (item 251) in the trench and overlying the capacitor dielectric layer (item 225), but does not specifically disclose wherein the first capacitor electrode has lower outer corners where a bottom surface of the trench meets sidewalls of the trench and has upper inner corners above the trench, and wherein the first capacitor electrode has a sidewall region extending continuously from the lower outer corners to the upper inner corners, the lower outer corners being rounded and the upper inner corners being square.
TSUI (Figs. 1A, 2C, 2T and associated text) discloses wherein the first capacitor electrode (item 212) has lower outer corners where a bottom surface of the trench (item 206) meets sidewalls of the trench (item 206) and has upper inner corners above the trench (item 206), and wherein the first capacitor electrode (item 212) has a sidewall region extending continuously from the lower outer corners to the upper inner corners, the lower outer corners being rounded and the upper inner corners being square.
It would have been obvious to modify the invention to include a first capacitor electrode having a sidewall region extending continuously from the lower outer corners to the upper inner corners, the lower outer corners being rounded and the upper inner corners being square, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regard to claim 11, Clevenger as modified by TSUI (Figs. 1A, 2C, 2T and associated text) discloses further comprising: a backside interconnect structure (item 240) disposed over the backside surface, the backside interconnect structure (item 240) including a metal line (items 246, 248, 252 or 254) over the backside surface; wherein the first and second capacitor electrodes (items 212 and 214 or 212 and 218) each include a collar that extends upward beyond an upper surface of the trench, the collar of the first capacitor electrode (item 212) having an upper surface that lies along a first plane that intersects the metal line (items 246, 248, 252 or 254), and the collar of the second capacitor electrode (items 214 o 218) having a lower surface that lies along a second plane lies that also intersects the metal line (items 246, 248, 252 or 254).
In regard to claim 12, Clevenger as modified by TSUI (Figs. 1A, 2C, 2T and associated text) discloses a doped semiconductor region (item 204) lining sidewalls of the trench and a bottom surface of the trench (item 206), the doped semiconductor region (item 204) coupled to the first or second capacitor electrode (items 212 and 214 or 212 and 218).
In regards to claim 15, Clevenger (Figs. 2A, 3A-3O and associated text) discloses a structure (Figs. 2A, 3O) comprising: a semiconductor substrate (item 110c) having a frontside surface (top surface of 110c) and a backside surface (bottom surface of item 110c); a frontside interconnect structure (items 110b pus 110a plus 125 plus 130) disposed beneath the frontside surface (top surface of 110c); a trench (item 210) disposed in the backside surface of the semiconductor substrate (item 110c), the trench (item 210) including a first capacitor electrode (item 221) in a lower portion of the trench (item 210), a capacitor dielectric layer (item 225) in the trench (item 210) and overlying the first capacitor electrode (item 221), and a second capacitor electrode (item 251) in the trench (item 210) and overlying the capacitor dielectric layer (item 225), but does not specifically disclose a backside interconnect structure disposed over the backside surface, the backside interconnect structure including a metal line; …wherein the first and second capacitor electrodes include first and second collars, respectively, that extend upward beyond an upper surface of the trench, the first collar of the first capacitor electrode having an upper surface that lies along a first plane that intersects the metal line, and the second collar of the second capacitor electrode having a lower surface that lies along a second plane lies that also intersects the metal line.
TSUI (Figs. 1A, 2C, 2T and associated text) discloses a backside interconnect structure (item 240) disposed over the backside surface, the backside interconnect structure (item 240) including a metal line (items 242, 246, 248 or 244); …wherein the first and second capacitor electrodes (items 212 and 214 or 212 and 218) include first and second collars, respectively, that extend upward beyond an upper surface of the trench, the first collar of the first capacitor electrode (item 212) having an upper surface that lies along a first plane that intersects the metal line (items 242, 246, 248 or 244), and the second collar of the second capacitor electrode (item 214 or 218) having a lower surface that lies along a second plane lies that also intersects the metal line (items 242, 246, 248 or 244).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of TSUI for the purpose of an electrical connection.
In regards to claim 16, TSUI (Figs. 1A, 2C, 2T and associated text) discloses wherein the first capacitor electrode (item 212) has lower outer corners where a bottom surface of the trench (item 206) meets sidewalls of the trench (item 206) and has upper inner corners above the trench (item 206), and wherein the first capacitor electrode (item 212) has a sidewall region extending continuously from the lower outer corners to the upper inner corners, the lower outer corners being rounded and the upper inner corners being square.
It would have been obvious to modify the invention to include a first capacitor electrode having a sidewall region extending continuously from the lower outer corners to the upper inner corners, the lower outer corners being rounded and the upper inner corners being square, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 17, TSUI (Figs. 1A, 2C, 2T and associated text) discloses a doped semiconductor region (item 204) lining sidewalls of the trench and a bottom surface of the trench, the doped semiconductor region (item 204) coupled to the first or second capacitor electrode (items 212, 214 or 218).
Claim(s) 13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clevenger et al. (Clevenger) (US 2007/0278619 A1) in view of TSUI et al. (TSUI) (US 2017/0271436 A1) as applied to claims 10-12 and 15-17 above, and further in view of Chang et al. (Chang) (US 2020/0176552 A1)
In regards to claim 13 and 18, Clevenger as modified by TSUI does not specifically disclose further comprising: a well region corresponding to an active device in the frontside surface of the semiconductor substrate, wherein a line parallel to the frontside and backside surfaces of the semiconductor substrate intersects both the well region and the doped semiconductor region.
Chang (Fig. 10 and associated text) discloses a well region (where item 1004 resides) corresponding to an active device (item 1004) in the frontside surface of the semiconductor substrate (item 104), wherein a line parallel to the frontside and backside surfaces of the semiconductor substrate (item 104) intersects both the well region where item 1004 resides) and the doped semiconductor region (item 104w) corresponding to the first capacitor electrode (item 114).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chang for the purpose of having a trench capacitor electrically coupled to a transistor.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 October 14, 2026
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