Prosecution Insights
Last updated: October 02, 2026
Application No. 18/754,942

INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING

Non-Final OA §102
Filed
Jun 26, 2024
Priority
Jun 10, 2021 — divisional of 12/051,638
Examiner
KOO, LAMONT B
Art Unit
Tech Center
Assignee
Tokyo Electron Limited
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
448 granted / 556 resolved
+20.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
51 currently pending
Career history
611
Total Applications
across all art units

Statute-Specific Performance

§103
65.9%
+25.9% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
6.5%
-33.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 556 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Teng et al. (US 2020/0105644) (hereafter Teng). Regarding claim 1, Teng discloses a method of microfabrication, the method comprising: forming an array of semiconductor devices 111 (Fig. 9, paragraph 0014) on a substrate 60 (Fig. 9, paragraph 0024), semiconductor devices 111 (Fig. 9) from the array of semiconductor devices 111 (Fig. 9) having one or more solid-state dielectric materials (113, 118’, and 61 in Fig. 9) surrounding the semiconductor devices 111 (Fig. 9); removing (see Fig. 10) at least a portion of the solid-state dielectric materials (113, 118’, and 61 in Fig. 9) surrounding the semiconductor devices 111 (Fig. 9) resulting in cavities 117A (Fig. 9, paragraph 0029) within the array of semiconductor devices 111 (Fig. 9); filling the cavities with a dielectric fluid (“cooling liquid (e.g., cooling water or other types of coolant)” in paragraph 0030) such that the dielectric fluid is in proximate thermal contact with the semiconductor devices 111 (Fig. 11); and forming a circulating mechanism (see paragraph 0030, wherein “an inlet I and an outlet O communicated with the flow channel”) to circulate the dielectric fluid (“cooling liquid” in paragraph 0030) from the cavities 117A (Fig. 11) to a heat dissipation region 121 (Fig. 11, paragraph 0030) and back through the cavities 117A (Fig. 11). Regarding claim 2, Teng further discloses the method of claim 1, wherein the solid-state dielectric materials (113, 118’, and 61 in Fig. 9; and see paragraph 0015, wherein “an oxide film, a nitride film, a dielectric film (such as benzocyclobutene (BCB), polybenzoxazole (PBO)), or the like,”) is silicon oxide or silicon nitride. Regarding claim 3, Teng further discloses the method of claim 1, wherein one or more access shafts 117A (Fig. 11, paragraph 0030) are formed on the solid-state dielectric materials (113 and 118’in Fig. 11) and the semiconductor devices 111 (Fig. 11). Regarding claim 4, Teng further discloses the method of claim 1, wherein removing (see Fig. 10) the at least a portion of the solid-state dielectric materials (113, 118’, and 61 in Fig. 9) surrounding the semiconductor devices 111 (Fig. 9) includes etching (see Fig. 10) solid-state dielectric materials (113, 118’, and 61 in Fig. 9) through the one or more access shafts (117A (Fig. 10). Regarding claim 5, Teng further discloses the method of claim 4, further comprising closing (see Fig. 12, wherein 117B is formed) the one or more access shafts 117A (Fig. 11) after removing (see Fig. 10) the at least a portion of the solid-state dielectric materials (113, 118’, and 61 in Fig. 9). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /L.B.K/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Jun 26, 2024
Application Filed
Aug 27, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
86%
With Interview (+5.2%)
2y 6m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 556 resolved cases by this examiner. Grant probability derived from career allowance rate.

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