DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/14/2026 has been entered.
Response to Arguments
Applicant’s arguments, filed on 9/14/2026, with respect to claims 1-12 and 21-25 have been fully considered and are persuasive. The final rejection on 1-12 and 21-25 issued on 8/12/2026 has been withdrawn.
Applicant’s arguments with respect to claim 13-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 1-12 and 21-25 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 1, prior art failed to disclose or fairly suggest a semiconductor device comprising, along with other recited claim limitations, a channel layer between the fin structure and the gate structure, wherein the channel layer is in the recess and directly contacts the fin structure, and the channel layer extends above the top-most surface of the fin structure beyond the region of the fin structure, as amended on 9/14/2026 an as argued on pages 6-11 of the remarks filed on 9/14/2026. Claims 2-12 and 23 depend from claim 1 and hence are allowed for the same reason therein.
Regarding Claim 21, prior art failed to disclose or fairly suggest a semiconductor device comprising, along with other recited claim limitations, an interfacial layer, wherein the interfacial layer comprises: a first portion extending parallel to the channel layer, and a second portion extending parallel to the sidewall, wherein the first portion comprises a different material from the second portion, as amended on 9/14/2026 an as argued on pages 6-11 of the remarks filed on 9/14/2026. Claims 22, 24 and 25 depend from claim 21 and hence are allowed for the same reason therein.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. 20160104775 in view of Huang et al. (20150001468) as applied above further in view of Shih et al. (20170162570) further in view of Ando et al. (20170053915)
Regarding Claim 13, in Figs. 7A, 7B, 8A, 8B and 9 and in paragraphs 0090 and 0102, Yoo et al. discloses a semiconductor device comprising: a fin structure FS1/FS2/FS3; a channel layer 120/121/140/141 over the fin structure, wherein the channel layer extends above a top-most surface of the fin structure FS1/FS2/FS3; a gate structure 161/163 over the channel layer, wherein a bottom-most surface of the gate structure is offset from the top-most surface of the fin structure (this is inherently so for two reason, the elements 171/173 which are source/drain regions which are part of the fin structure are in raised configuration and hence there is an elevational difference , i.e offset between the top surface of 171/173 and bottom most surface of gate structure 161/163. Furthermore, the claimed offset is also inherently present since there are layers 151/153 between the gate structure 161/163 and the top surface of fin FS1/FS2/FS3 and spacers SP along sidewalls of the gate structure, wherein the channel layer 120/121/140/141 is between the spacers SP and the fin structure FS1/FS2/FS3. Yoo et al. fails to disclose the newly added limitation with respect to recessed fin and channel layer. However, Huang et al discloses a FET device where in Figs. 27A-27B, 28A-28B and 30A-30B, paragraph 0063 and 0065 the required recessed fin and channel are disclosed as element 112 and 64.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the recessed fin and channel in Yoo et al. as taught by Huang et al. for reliability and speed purposes.
Yoo et al. and Huang et al. combination fails to disclose the limitation where, the gate structure comprising a water-soluble interfacial layer, and the water-soluble interfacial layer directly contacts the channel layer. However, Shih et al. discloses a semiconductor device where in Fig. 2 element 26, and in paragraphs 0023, 0025 and 0027, Shih et al. discloses that, the gate structure 29/27/26 comprising a water-soluble interfacial layer 26, and the water-soluble interfacial layer 26 directly contacts the channel layer 4. (Please note that the material of interfacial layer 26 is a water soluble oxide material, i.e. germanium oxide, which matches the material of the claimed limitation, see paragraph 0027 of Shih et al.)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required interfacial layer in Yoo et al. and Huang et al. combination as taught by Shih et al. order to have compatibility between the channel layer and the gate dielectric materials.
Yoo, Huang and Shih combination fails to disclose the newly added limitation of
“the water-soluble interfacial layer directly contacts the channel layer, and the water-soluble interfacial layer comprises lanthanum oxide”. However, such limitation is disclosed in Fig. 1, paragraph 0040 as elements 31a/31b (with 1-10 or more likely 2-6 angstrom thickness) and element 15.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claim invention to have the required lanthanum oxide layer IL in Yoo, Huang and Shih combination as taught by Ando et al. in order to have a semiconductor device having excellent electrical properties and speed.
Regarding Claim 14, in paragraph 0066 of Yoo et al, the channel layer 120/121/140/141 comprises germanium.
Regarding Claim 15, in Yoo et al., a source/drain feature 170/171 in the fin structure FS1/FS2/FS3, wherein the channel layer 120/121/140/141 contacts the source/drain feature 170/171.
Examiner is including Chugzik et al. (2011/0248350) and Pae et al. (20080070367) as pertinent prior art references that are not relied upon but that disclose dual gate dielectrics with lanthanum oxide dielectric layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/16/2026
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