DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 and 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. 20160104775 in view of Huang et al. (2015/0001468)
Regarding Claim 1, in Figs. 7A, 7B, 8A, 8B and 9 and in paragraphs 0090 and 0102, Yoo et al. discloses a semiconductor device comprising: a fin structure FS1/FS2/FS3; a gate structure 161/163 over a region of the fin structure, wherein a bottom-most surface of the gate structure 161/163 is offset from a top-most surface of the fin structure beyond the region of the fin structure FS1/FS2/FS3 (this is inherently so for two reason, the elements 171/173 which are source/drain regions which are part of the fin structure are in raised configuration and hence there is an elevational difference , i.e offset between the top surface of 171/173 and bottom most surface of gate structure 161/163. Furthermore, the claimed offset is also inherently present since there are layers 151/153 between the gate structure 161/163 and the top surface of fin FS1/FS2/FS3); and a channel layer 120/121/140/141 between the fin structure FS1/FS2/FS3 and the gate structure 161/163 (this is so because of the spacer pattern 121), wherein the channel layer 120/121/140/141 extends above the top-most surface of the fin structure (i.e. the region between the raised source/drain regions 171/173) beyond the region of the fin structure (again the region between the raised source/drain region 171/173). Yoo et al. fails to disclose the newly added limitation with respect to recessed fin and channel layer. However, Huang et al discloses a FET device where in Figs. 27A-27B, 28A-28B and 30A-30B, paragraph 0063 and 0065 the required recessed fin and channel are disclosed as element 112 and 64.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the recessed fin and channel in Yoo et al. as taught by Huang et al. for reliability and speed purposes.
Regarding Claim 2, Yoo et al discloses spacers SP along sidewalls of the gate structure 161/163 (also see paragraph 0094).
Regarding Claim 3, in Yoo et al, the channel layer 120/121/140/141 is between the spacers SP and the fin structure FS1/FS2/FS3.
Regarding Claim 4, in Yoo et al, a first source/drain (S/D) feature 171/173 in the fin structure FS1/FS2/FS3; and a second S/D feature 171/173 in the fin structure.
Regarding Claim 5, in Yoo et al, the first S/D feature 171/173 is a raised S/D feature.
Regarding Claim 6, in Yoo et al, channel layer 120/121/140/141 is between the first S/D feature 171/173 and the second S/D feature 171/173.
Regarding Claim 7, in Yoo et al., the channel layer 120/121/140/141 (directly and/or indirectly) contacts the first S/D feature 171/173.
Regarding Claim 10, in paragraph 00066 of Yoo et al, the channel layer 120/121/140/141 comprises germanium.
Regarding Claim 11, in paragraph 0066 of Yoo et al., a germanium concentration of the channel layer 120/121/140/141 ranges from about 15% to about 95%.
Regarding Claim 12, in paragraphs 0090 and 0101 of Yoo et al., a thickness of the channel layer ranges from about 4 nanometers (nm) to about 40 nm.
Claims 8, 9, 13-15 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. 20160104775 in view of Huang et al. (20150001468) as applied above further in view of Shih et al. (20170162570).
Regarding Claim 8, Yoo et al. and Huang et al. combination discloses everything except to disclose the required water-soluble interfacial layer that directly contacts the channel layer. However, Shih et al. discloses a semiconductor device where in Fig. 2 element 26, and in paragraphs 0023, 0025 and 0027 the required water-soluble interfacial layer is disclosed. (Please note that the material of interfacial layer 26 is a water soluble oxide material, i.e. germanium oxide, which matches the material of the claimed limitation, see paragraph 0027 of Shih et al.)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required interfacial layer in Yoo et al. and Yoo et al. combination as taught by Shih et al. in order to have compatibility between the channel layer and the gate dielectric materials.
Regarding Claim 9, in Fig. 2 of Shih et al., interfacial layer 26 directly contacts channel layer 2
Regarding Claim 13, in Figs. 7A, 7B, 8A, 8B and 9 and in paragraphs 0090 and 0102, Yoo et al. discloses a semiconductor device comprising: a fin structure FS1/FS2/FS3; a channel layer 120/121/140/141 over the fin structure, wherein the channel layer extends above a top-most surface of the fin structure FS1/FS2/FS3; a gate structure 161/163 over the channel layer, wherein a bottom-most surface of the gate structure is offset from the top-most surface of the fin structure (this is inherently so for two reason, the elements 171/173 which are source/drain regions which are part of the fin structure are in raised configuration and hence there is an elevational difference , i.e offset between the top surface of 171/173 and bottom most surface of gate structure 161/163. Furthermore, the claimed offset is also inherently present since there are layers 151/153 between the gate structure 161/163 and the top surface of fin FS1/FS2/FS3 and spacers SP along sidewalls of the gate structure, wherein the channel layer 120/121/140/141 is between the spacers SP and the fin structure FS1/FS2/FS3. Yoo et al. fails to disclose the newly added limitation with respect to recessed fin and channel layer. However, Huang et al discloses a FET device where in Figs. 27A-27B, 28A-28B and 30A-30B, paragraph 0063 and 0065 the required recessed fin and channel are disclosed as element 112 and 64.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the recessed fin and channel in Yoo et al. as taught by Huang et al. for reliability and speed purposes.
Yoo et al. and Huang et al. combination fails to disclose the limitation where, the gate structure comprising a water-soluble interfacial layer, and the water-soluble interfacial layer directly contacts the channel layer. However, Shih et al. discloses a semiconductor device where in Fig. 2 element 26, and in paragraphs 0023, 0025 and 0027, Shih et al. discloses that, the gate structure 29/27/26 comprising a water-soluble interfacial layer 26, and the water-soluble interfacial layer 26 directly contacts the channel layer 4. (Please note that the material of interfacial layer 26 is a water soluble oxide material, i.e. germanium oxide, which matches the material of the claimed limitation, see paragraph 0027 of Shih et al.)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required interfacial layer in Yoo et al. and Huang et al. combination as taught by Shih et al. order to have compatibility between the channel layer and the gate dielectric materials.
Regarding Claim 14, in paragraph 0066 of Yoo et al, the channel layer 120/121/140/141 comprises germanium.
Regarding Claim 15, in Yoo et al., a source/drain feature 170/171 in the fin structure FS1/FS2/FS3, wherein the channel layer 120/121/140/141 contacts the source/drain feature 170/171.
Regarding Claim 21, in Figs. 7A, 7B, 8A, 8B and 9 and in paragraphs 0090 and 0102, Yoo et al. discloses a semiconductor device comprising: a fin structure FS1/FS2/FS3; a channel layer 120/121/140/141 over a top-most surface of the fin structure, wherein an interface exists between the channel layer and the fin structure; a gate structure 161/163 over the channel layer, wherein the gate structure comprises: spacers SP having a sidewall extending in a direction perpendicular to the top-most surface of the fin structure. Yoo et al. fails to disclose the newly added limitation with respect to recessed fin and channel layer. However, Huang et al discloses a FET device where in Figs. 27A-27B, 28A-28B and 30A-30B, paragraph 0063 and 0065 the required recessed fin and channel are disclosed as element 112 and 64.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the recessed fin and channel in Yoo et al. as taught by Huang et al. for reliability and speed purposes.
Yoo et al. and Huang et al. combination fails to disclose the limitation of an interfacial layer, wherein the interfacial layer comprises: a first portion extending parallel to the channel layer, and a second portion extending parallel to the sidewall. However, Shih et al. discloses a semiconductor device where in Fig. 2, the interfacial layer 26 is disclosed. With respect to first and second portions of the interfacial layer, this refers to U-shaped interfacial layer (see Fig. 4 and paragraph 0048 of the application). The U-shaped interfacial layer (and hence the first portion and the second portion of the interfacial layer) is disclosed by Shih in paragraph 0037 last 4 lines.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required interfacial layer in Yoo et al. and Huang et al. combination as taught by Shih et al. in order to have compatibility between the channel layer and the gate dielectric materials.
Regarding Claim 22, in paragraphs 0070-075 of Yoo et al. and paragraph 0025 of Shih et al, the spacers include germanium atoms.
Regarding Claim 23, in Shih et al., paragraph 0037, the first portion comprises a same material as the second portion.
Regarding Claim 24, in paragraphs 0071 and 0075 of Yoo et al. and paragraph 0023 of Shih et al., the spacers include silicon atoms.
Regarding Claim 25, in paragraphs 0022 and 0066 of Yoo et al. in conjunction with paragraphs 0023-0025, 0027,0030 and 0034 of Shih et al, the first portion comprises a different material from the second portion.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 6/10/2026
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