Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 6/29/2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. A legible copy of NPL #1: G. Sisto (2021) has not been provided. All other citations in this IDS have been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed subject matter of claim 15 “wherein the second integrated device structure is wider than the first integrated device structure” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. More specifically: claim 1 requires a particular “bump” configuration, and the figures do not show this configuration combinable with the claimed “wider” configuration.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 9 is objected to because of the following informalities: “the second integrated device” in line 2. For the sake of compact prosecution, claim 9 is interpreted in the instant Office action as follows: “the second integrated device” is found to be a typographical error and is believed to be equivalent to “the second integrated device structure” based on antecedence for this term in claim 1, line 4; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: “the second integrated device” in line 2. For the sake of compact prosecution, claim 10 is interpreted in the instant Office action as follows: “the second integrated device” is found to be a typographical error and is believed to be equivalent to “the second integrated device structure” based on antecedence for this term in claim 1, line 4; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 11 is objected to because of the following informalities: “the second integrated device” in line 2. For the sake of compact prosecution, claim 11 is interpreted in the instant Office action as follows: “the second integrated device” is found to be a typographical error and is believed to be equivalent to “the second integrated device structure” based on antecedence for this term in claim 1, line 4; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 12 is objected to because of the following informalities: “the second integrated device” in line 2. For the sake of compact prosecution, claim 12 is interpreted in the instant Office action as follows: “the second integrated device” is found to be a typographical error and is believed to be equivalent to “the second integrated device structure” based on antecedence for this term in claim 1, line 4; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 14 is objected to because of the following informalities: “the first integrated device” in line 1. For the sake of compact prosecution, claim 14 is interpreted in the instant Office action as follows: “the first integrated device” is found to be a typographical error and is believed to be equivalent to “the first integrated device structure” based on antecedence for this term in claim 1, line 2; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 11, and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation “the first backside interconnect level” in line . There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 4 is interpreted in the instant Office action as follows: “the first backside interconnect level” is equivalent to “a first backside interconnect level” based on [0016] of the originally filed Specification. This interpretation is to be confirmed by applicant in the next office action.
Regarding claim 11, “the first power bump” in line 6 is unclear whether it is referring to the same “the at least one first power bump” recited in line 4, “the third bump” recited in line 6, “the at least one second power bump” recited in claim 1 line 1, or some other bump. More specifically, the claimed “voltage” configuration in combination with the difference in term phrasing renders this limitation unclear. For the sake of compact prosecution, claim 11 is interpreted in the instant Office action as follows: “the first bump” in line 6 is equivalent to “the at least one second power bump”. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 12, “the first power bump” in line 6 is unclear whether it is referring to the same “the at least one first power bump” recited in line 4, “the third bump” recited in line 6, “the at least one second power bump” recited in claim 1 line 1, or some other bump. More specifically, the claimed “voltage” configuration in combination with the difference in term phrasing renders this limitation unclear. For the sake of compact prosecution, claim 12 is interpreted in the instant Office action as follows: “the first bump” in line 6 is equivalent to “the at least one second power bump”. This interpretation is to be confirmed by applicant in next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 10-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu (US 20240063160 A1).
Regarding claim 1, Lu discloses a stacked semiconductor structure (Fig. 10) comprising:
a first integrated device structure (101a) having a first frontside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) and a first backside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) wherein the first backside comprises a first backside power distribution network ([0050]: “power distribution network”);
a seconded integrated device structure (101b) having a second frontside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) and a second backside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) wherein the second backside comprises a second backside power distribution network ([0024]: “power distribution network…backside”);
a plurality of hybrid bond connections (126a/126b, See annotated figure; [0027]: “dielectric-to-dielectric and metal-to-metal bonding” is consistent with the ordinary and customary definition, and Applicant’s definition of “hybrid bond connections”) between (sandwiched “between”) the first frontside and the second frontside;
at least one first power bump (102 in combination with 321 and 321´, See annotated figure, See annotated figure) on the first frontside configured to deliver power to the first backside power distribution network (Fig. 10 shows the cited bump electrically connected to the network, thus it is “configured to deliver power to…”); and
at least one second power bump (102, See annotated figure) on the second backside configured to deliver power to the second backside power distribution network ([0024]: “power and ground signals can be provided to the device regions 121b along a shorter path from the back side of the substrate 103b”, thus it is “configured to deliver power to…”).
Illustrated below is a marked and annotated figure of Fig. 10 of Lu.
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Regarding claim 2, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) wherein the first backside further comprises a heat distribution structure (1001/1002).
Regarding claim 3, Lu discloses the stacked semiconductor structure of Claim 2 (Fig. 10) wherein the heat distribution structure is metallic ([0050]: “interconnect wirings 1022” in combination with [0018]: “the material of the first interconnect wirings 122a may be copper (Cu) or other suitable metallic material”).
Regarding claim 4 as noted in the 112(b) rejection, Lu discloses the stacked semiconductor structure of Claim 2 wherein the heat distribution structure comprises via and line stacked structures (122a) that pass through a first backside interconnect level (104a).
Regarding claim 7, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) wherein the first power bump is directly on the first frontside (the cited collection is “directly on”).
Regarding claim 10, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) further comprising: a third bump (102, See annotated figure) on the second integrated device; wherein the first integrated device structure is configured to receive a first voltage from the at least one first power bump (Fig. 10 shows electrical connection from 102 all the way to 1001, thus at least some kind of “voltage” would be received); and wherein the first integrated device structure is configured to receive a second voltage from the third bump ([0024]: “The power distribution network (PDN) circuitry is configured to transmit power and ground signals to the devices in each semiconductor wafers 101a and 101b”).
Regarding claim 11 as noted in the 112(b) rejection, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) further comprising: a third bump (102, See annotated figure) on the second integrated device; and wherein the first integrated device structure is configured to receive a first voltage only from one of the at least one first power bump (Fig. 10 shows electrical connection from 102 all the way to 1001, thus at least some kind of “voltage” would be received); wherein the first integrated device structure is configured to receive a second voltage from the at least one second power bump and the third bump ([0024]: “The power distribution network (PDN) circuitry is configured to transmit power and ground signals to the devices in each semiconductor wafers 101a and 101b”).
Regarding claim 13, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) wherein the first integrated device structure is wider (“wider” to accommodate 321) than the second integrated device structure.
Regarding claim 14, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) wherein the first integrated device is a wafer ([0024]: “semiconductor wafers”).
Regarding claim 17, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) wherein a first bottom (See dashed reference line) of the first power bump is at a same level from a second bottom (See dashed reference line) of the second power bump.
Regarding claim 18, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) wherein a first bottom of the first power bump is at a different level from a second bottom of the second power bump (See dotted reference lines, within the breadth of the claim as written).
Regarding claim 19, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) further comprising at least one signal input/out bump (3rd Bump, See annotated figure; [0024]: “power and ground signals”) on the second backside.
Note that claim 1 was previously addressed above, however, it’s being addressed differently here based on the reading of the reference, particularly to the assignment of the integrated device structures in order to address the dependent claims 8-9, 12, and 15-16.
Regarding claim 1, Lu discloses a stacked semiconductor structure (Fig. 11) comprising:
a first integrated device structure (101b) having a first frontside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) and a first backside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) wherein the first backside comprises a first backside power distribution network ([0024]: “power distribution network…backside”);
a seconded integrated device structure (101a) having a second frontside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) and a second backside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) wherein the second backside comprises a second backside power distribution network ([0051]: “power distribution network…backside”);
a plurality of hybrid bond connections (126a/126b, See annotated figure; [0027]: “dielectric-to-dielectric and metal-to-metal bonding” is consistent with the ordinary and customary definition, and Applicant’s definition of “hybrid bond connections”) between (sandwiched “between”) the first frontside and the second frontside;
at least one first power bump (102) on the first frontside (indirectly “on”) configured to deliver power to the first backside power distribution network ([0051]: “configured to transmit”); and
at least one second power bump (another 102) on the second backside configured to deliver power to the second backside power distribution network ([0051]: “configured to transmit”).
Illustrated below is a marked and annotated figure of Fig. 11 of Lu.
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Regarding claim 8, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 11) wherein the at least one first power bump on the first frontside is configured to deliver all power to first integrated device structure to the first backside power distribution network (there are no other illustrated bumps or possible paths for power supply, and no other bumps or possible paths are described in [0051]).
Regarding claim 9, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 11) further comprising: a third bump (yet another 102) on the second integrated device; and wherein the first integrated device structure is configured to receive a first voltage from the at least one first power bump and from the third bump ([0051]: “configured to transmit power and ground signals to the devices in semiconductor die 101a and/or the semiconductor die 101b”).
Regarding claim 12, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 11) further comprising: a third bump (yet another 102) on the second integrated device; and wherein the first integrated device structure is configured to receive a first voltage only from third bump (there is at least one electrical path illustrated only routing from 102 to 101b); wherein the first integrated device structure is configured to receive a second voltage from the at least one second power bump and the third bump ([0051]: “configured to transmit power and ground signals to the devices in semiconductor die 101a and/or the semiconductor die 101b”).
Regarding claim 15, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 11) wherein the second integrated device structure is wider than the first integrated device structure (“wider” to accommodate 321).
Regarding claim 16, Lu discloses the stacked semiconductor structure of Claim 15 (Fig. 11) wherein the second integrated device structure is centered on the first integrated device structure (the figure shows “centered”).
Claims 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu, with evidence provided by Takeuchi (US 20160009090 A1). MPEP 2112 (III).
Regarding claim 5, Lu discloses the stacked semiconductor structure of Claim 1 (Fig. 10) wherein the first backside power distribution network comprises a high thermal conductivity dielectric ([0050]: “1001 may be similar to that of the interconnect structures 104a, 104b, 105 and 106” in combination with [0018]: “may be…silicon nitride”. Note: the claimed “high thermal conductivity” is a well-known characteristic of SiN with respect to other materials, such as SiO. See additional remarks below regarding thermal conductivity.).
Regarding the claimed thermal conductivity configuration “high thermal conductivity”: Lu teaches materials ([0018]: “silicon nitride”) capable of reading on the claim, but fails to explicitly teach thermal conductivity characteristics of these materials. Takeuchi provides evidence that the thermal conductivity characteristics of these materials (Lu) is consistent with the claim ([0036]: “SiN is higher in thermal conductivity than SiO”). Therefore, the claimed thermal conductivity configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it is a characteristic inherently within the prior art (Lu). MPEP 2112.
Regarding claim 6, Lu discloses the stacked semiconductor structure of Claim 5 (Fig. 10) wherein the high thermal conductivity dielectric comprises one or more of silicon nitride (Lu: [0018]: “silicon nitride” was relied upon in the claim 5 rejection), aluminum nitride, hexagonal boron nitride, and nanocomposites.
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu, with evidence provided by Takeuchi. MPEP 2112 (III).
Regarding independent claim 20, Lu discloses a method of forming a semiconductor structure (Fig. 10), comprising:
providing a first integrated device structure (101a) having a first frontside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) and a first backside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) wherein the first backside comprises a first power distribution network ([0050]: “power distribution network”);
providing a second integrated device structure (101b) having a second frontside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) and a second backside (See annotated figure, a side/portion, not limited to a surface, consistent with Applicant’s use of this term) wherein the second backside comprises a second power distribution network ([0024]: “power distribution network…backside”);
hybrid bonding the first frontside and the second frontside (126a/126b, See annotated figure; [0027]: “dielectric-to-dielectric and metal-to-metal bonding” is consistent with the ordinary and customary definition, and Applicant’s definition of “hybrid bond connections”) to form a stacked structure;
forming at least one first power bump (102 in combination with 321 and 321´, See annotated figure) directly on the first frontside configured to deliver power to the first backside power distribution network (Fig. 10 shows the cited bump electrically connected to the network, thus it is “configured to deliver power to…”); and
forming at least one second power bump (102, See annotated figure) on the second backside configured to deliver power to the second backside power distribution network ([0024]: “power and ground signals can be provided to the device regions 121b along a shorter path from the back side of the substrate 103b”, thus it is “configured to deliver power to…”);
wherein the first backside further comprises a metallic heat distribution structure (1001/1002; [0050]: “interconnect wirings 1022” in combination with [0018]: “the material of the first interconnect wirings 122a may be copper (Cu) or other suitable metallic material”) and a dielectric ([0050]: “1001 may be similar to that of the interconnect structures 104a, 104b, 105 and 106” in combination with [0018]: “may be…silicon nitride”) having a thermal conductivity greater than the thermal conductivity of silicon dioxide (Note: this is a well-known characteristic of SiN with respect to SiO. See additional remarks below regarding thermal conductivity.).
Regarding the claimed thermal conductivity configuration “a thermal conductivity greater than the thermal conductivity of silicon dioxide”: Lu teaches materials ([0018]: “silicon nitride”) capable of reading on the claim, but fails to explicitly teach thermal conductivity characteristics of these materials. Takeuchi provides evidence that the thermal conductivity characteristics of these materials (Lu) is consistent with the claim ([0036]: “SiN is higher in thermal conductivity than SiO”). Therefore, the claimed thermal conductivity configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it is a characteristic inherently within the prior art (Lu). MPEP 2112.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
