Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-7, 9, 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hineman et al. (US 2003/0203510 A1) in view of Brankner et al. (EP 0855739 A1).
Regarding claim 1, Hineman teaches a method for planarizing a surface of a semiconductor device (forming an MRAM device and planarizing a continuous first insulator/interlevel dielectric layer using chemical-mechanical planarization; paragraphs [0011], [0033]).
Hineman further teaches providing a substrate defining a memory region, wherein a memory component is disposed on the substrate and located in the memory region (forming a plurality of individual magnetic memory devices on a substrate, including protrusions comprising magneto resistive memory layers, and describing one TMR memory cell stud after patterning and etching into an array of memory cells; paragraphs [0011], [0012], [0032]).
Hineman also teaches forming a dielectric layer to cover the memory component, wherein the dielectric layer comprises a protruding portion corresponding to the memory component (forming a continuous first insulator/interlevel dielectric layer over the substrate and the magnetic memory devices, and forming a layer of insulating material over protrusions comprising magneto resistive memory layers, spacers, and the substrate, such that the deposited dielectric layer covers and corresponds to the protruding memory cell structure; paragraphs [0011], [0012], [0033]).
Hineman teaches removing the sidewall structure to planarize the dielectric layer (planarizing the continuous first insulator/interlevel dielectric layer, preferably using chemical-mechanical planarization, to expose the top of the capping layer over the memory cell; paragraph [0033]).
Hineman does not expressly teach etching a portion of the protruding portion to form a sidewall structure, wherein the sidewall structure comprises an etched side surface, and an included angle between the etched side surface of the sidewall structure and an etched top surface of the protruding portion is an obtuse angle.
Brankner teaches etching a portion of the protruding portion to form a sidewall structure (performing a tapered dielectric etch process prior to CMP, including applying a reverse moat pattern over trench-fill dielectric material and etching the trench-fill material using the pattern to remove excess dielectric material before CMP; page 2, lines 32-39).
Brankner continues to teach wherein the sidewall structure comprises an etched side surface, and an included angle between the etched side surface of the sidewall structure and an etched top surface of the protruding portion is an obtuse angle (partially removing exposed trench-fill dielectric material using a first anisotropic etch as shown in FIG. 6, and then performing an isotropic etch as shown in FIG. 7 to remove a significant portion of excess dielectric material before CMP and form a tapered etched dielectric profile; page 3, lines 27-34; page 4, lines 14-23; FIGS. 6-7).
Brankner further teaches forming the tapered etched dielectric profile by increasing lateral etching during the isotropic etch step (teaching that increasing oxygen increases the horizontal etch rate in the isotropic etch step; page 6, lines 16-21).
Brankner teaches removing the sidewall structure to planarize the dielectric layer (performing CMP after the tapered dielectric etch process, wherein less trench-fill material remains over dense areas to be removed by CMP, allowing CMP planarization to be accomplished in less polish time and with more uniformity; page 4, lines 14-23; page 6, lines 28-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hineman to include etching a portion of the protruding portion to form a sidewall structure, wherein the sidewall structure comprises an etched side surface, and an included angle between the etched side surface of the sidewall structure and an etched top surface of the protruding portion is an obtuse angle, as taught by Brankner, because Brankner teaches that a tapered dielectric etch process performed prior to CMP reduces the amount of dielectric material to be polished, partially planarizes the structure, reduces polish time, and improves CMP uniformity (page 2, lines 32-39; page 4, lines 14-23; page 6, lines 28-32). The use of Brankner’s tapered dielectric etch process in Hineman’s MRAM dielectric planarization method would have been the use of a known technique to improve a similar semiconductor dielectric planarization method in the same way, with predictable results. See MPEP § 2141, subsection III(C).
Regarding claim 4, modified Hineman teaches the method of claim 1. Modified Hineman also teaches wherein the sidewall structure further comprises a non-etched side surface disposed opposite to the etched side surface, and an inclined degree of the non-etched side surface is smaller than an inclined degree of the etched side surface (Brankner teaches forming reverse moat pattern 40 from an etch-resistant material to protect low areas 14 and trench corners while exposed high areas 18 are etched, partially removing exposed trench-fill material 16 by a first anisotropic etch as shown in FIG. 6, and then performing an isotropic etch as shown in FIG. 7 to remove excess trench-fill material and form a tapered etched side surface opposite a protected, less-inclined side surface of the remaining dielectric material; page 3, lines 19-34; page 4, lines 14-23; FIGS. 5-7).
Regarding claim 5, modified Hineman teaches the method of claim 1. Modified Hineman further teaches wherein etching the portion of the protruding portion comprises forming a recess, the sidewall structure is adjacent to the recess, and the etched side surface faces the recess (Brankner teaches etching exposed trench-fill dielectric material using reverse moat pattern 40, thereby partially removing exposed trench-fill material and leaving remaining tapered dielectric material adjacent to the removed/recessed region; page 3, lines 27-34; page 4, lines 14-23; FIGS. 6-7).
Regarding claim 6, modified Hineman teaches the method of claim 1. Modified Hineman teaches forming a patterned mask to cover the dielectric layer, wherein the patterned mask comprises an opening corresponding to the portion of the protruding portion; and etching the portion of the protruding portion to form the recess (Brankner teaches applying reverse moat pattern 40 over trench-fill dielectric material and etching exposed trench-fill material using the pattern; page 2, lines 32-39; page 3, lines 27-34; FIGS. 5-7).
Regarding claim 7, modified Hineman teaches the method of claim 1. modified Hineman teaches the method of claim 1. Brankner further teaches wherein the portion of the protruding portion is etched by a dry etching process (etching trench-fill dielectric material using etch chemistries including Ar, CF4, CHF3, and O2 during anisotropic and isotropic etch steps before CMP; page 4, lines 10-23).
Regarding claim 9, modified Hineman teaches the method of claim 1. Hineman continues to teach wherein removing the sidewall structure to planarize the dielectric layer is by a chemical mechanical polishing process (planarizing the continuous first insulator/interlevel dielectric layer, preferably using chemical-mechanical planarization, to expose the top of the capping layer over the memory cell; paragraph [0033]).
Regarding claim 11, modified Hineman teaches the method of claim 1. Hineman also teaches wherein the memory component is a magnetic tunnel junction component (describing one TMR memory cell stud after patterning and etching into an array of memory cells, and describing the structure as a multi-layer magnetic memory cell, preferably a TMR memory cell; paragraphs [0032], [0046]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hineman in view of Brankner, as applied to claim 1 above, and further in view of Bielefeld et al. (US 2008/0073748 A1).
Modified Hineman teaches the method of claim 1 as discussed above.
Modified Hineman does not expressly teach wherein the included angle is greater than or equal to 100 degrees and less than or equal to 140 degrees.
Bielefeld teaches wherein the included angle is greater than or equal to 100 degrees and less than or equal to 140 degrees (patterning sacrificial dielectric layer 504 to form patterned sacrificial dielectric layer 506 having a series of trenches formed therein, wherein the series of trenches have flared profiles with a flared angle θ between 90 degrees and 155 degrees, and in a specific embodiment the flared angle is in the range of 105 degrees to 135 degrees; paragraph [0033]).
Bielefeld further teaches forming the included angle by etching a dielectric layer (patterning sacrificial dielectric layer 504 using an anisotropic etch process or a vertical dry/plasma etch process comprising fluorocarbons, wherein the flared profile is formed during patterning of sacrificial dielectric layer 504 with an anisotropic plasma etch process; paragraphs [0032]-[0033]). Therefore, Bielefeld teaches predictable operating ranges for the anisotropic etching of Hineman for forming the tapered dielectric.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify modified Hineman to include wherein the included angle is greater than or equal to 100 degrees and less than or equal to 140 degrees, as taught by Bielefeld, because Bielefeld teaches forming etched dielectric trench profiles having a flared angle of 105 degrees to 135 degrees by controlling the dielectric etch profile during plasma etching. Selecting Bielefeld’s disclosed flared angle range for the tapered etched dielectric profile of modified Hineman would have been a selection of a known etched dielectric sidewall angle range that overlaps the claimed range and would predictably form a tapered/flared etched dielectric profile. See MPEP § 2144.05.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hineman in view of Brankner applied to claim 1 above, and further in view of Kim et al. (US 9,214,548 B1).
Modified Hineman teaches the method of claim 1 as discussed above.
Modified Hineman does not expressly teach wherein the etched side surface comprises a first portion and a second portion from bottom to top, and an inclined degree of the first portion is smaller than an inclined degree of the second portion.
Kim teaches wherein the etched side surface comprises a first portion and a second portion from bottom to top, and an inclined degree of the first portion is smaller than an inclined degree of the second portion (forming a trench insulation layer having dual-sloped sidewalls, wherein a first slope of upper sidewalls is different from a second slope of lower sidewalls, the first slope is greater than the second slope, a first angle of the upper sidewall is about 55 degrees to about 59 degrees, and a second angle of the lower sidewall is about 24 degrees to about 28 degrees; Col. 5, lines 15-41).
Kim further teaches that the dual-sloped sidewall profile reduces sharpness of lower corners of the trench insulation layer (teaching that the sharpness of lower corners of the trench insulation layer may be dulled because of the presence of the lower sidewall; Col. 5, lines 15-41).
Brankner further teaches there are several concerns that occur in removing the excess dielectric material 18. Due to the nature of the CMP process, the removal rate of the excess dielectric material 18 is dependent on the feature size and the local pattern density. This variation in removal rate can result in damage to the silicon under isolated moat features or incomplete removal of the oxide over large/dense moat features. (Note: moat is the area under the nitride stop layer in FIG. 1.) The pattern density effect and the polish nonuniformity result in nonuniform field oxide thickness within the product. By controlling the size and shape of the taper, the removal rate can be controlled and differences in pattern density can be compensated for (pages 2-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify modified Hineman to include wherein the etched side surface comprises a first portion and a second portion from bottom to top, and an inclined degree of the first portion is smaller than an inclined degree of the second portion, as taught by Kim, because Kim teaches a semiconductor insulation structure having a dual-sloped sidewall profile in which the lower sidewall has a smaller slope than the upper sidewall and the dual-sloped profile reduces the sharpness of lower corners. Applying Kim’s known dual-sloped sidewall profile to the tapered etched dielectric profile of modified Hineman would have been the use of a known sidewall-profile technique controlling the size and shape of the taper to compensate for pattern density to improve a similar semiconductor dielectric/insulation structure in the same way, with predictable results. See MPEP § 2141 III(C).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hineman in view of Brankner applied to claim 7 above, and further in view of Lindley et al. (US 6,326,307 B1).
Modified Hineman teaches the method of claim 7 as discussed above.
Modified Hineman does not expressly teach wherein etching the portion of the protruding portion comprises introducing an etching gas, wherein a portion of the etching gas reacts to form a protective layer covering a bottom of the etched side surface; and removing the protective layer.
Lindley teaches introducing an etching gas (admitting an etching gas into an etch chamber through a dielectric showerhead electrode; Col. 5, lines 5-19).
Lindley also teaches wherein a portion of the etching gas reacts to form a protective layer covering a bottom of the etched side surface (performing a main etch using low-F/C fluorocarbon C4F8, wherein C4F8 provides bottom and sidewall protection, and wherein low-F/C fluorocarbon results in a polymerizing plasma; Col. 5, lines 49-70; Col. 6, lines 1-2).
Lindley further teaches the protective layer protects the etched side surface (describing polymer overlying the oxide sidewall, wherein the oxide sidewall becomes exposed and etched if the depth of striations exceeds the thickness of the polymer layer; Col. 4, lines 48-58).
Lindley teaches removing the protective layer (removing remaining photoresist and deposited polymer through dry and/or wet stripping processes, generically known as stripping or ashing; Col. 4, lines 5-14; further teaching that, after the main oxide etch, the polymer and photoresist are ashed; Col. 4, lines 59-70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify modified Hineman to include wherein etching the portion of the protruding portion comprises introducing an etching gas, wherein a portion of the etching gas reacts to form a protective layer covering a bottom of the etched side surface; and removing the protective layer, as taught by Lindley, because Lindley teaches that fluorocarbon-based dielectric etching forms a polymerizing plasma that provides bottom and sidewall protection during dielectric etching, and that the deposited polymer is removed after etching by stripping or ashing. Applying Lindley’s known fluorocarbon-polymer protection and removal technique to the dry dielectric etch process of modified Hineman would have been the use of a known technique to improve a similar semiconductor dielectric etching method in the same way, with predictable results. See MPEP § 2141 , subsection III(C).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hineman in view of Brankner as applied to claim 1 above, and further in view of Wang et al. (US 2021/0151666 A1).
Modified Hineman teaches the method of claim 1 as discussed above.
Modified Hineman does not expressly teach wherein the dielectric layer comprises an ultra-low dielectric constant dielectric material.
Wang teaches wherein the dielectric layer comprises an ultra-low dielectric constant dielectric material (forming an ultra low-k dielectric layer 82 serving as another IMD layer 84 to cover passivation layer 74, wherein the ultra low-k dielectric layer 82 preferably surrounds MTJs 62, 72, and wherein the ultra low-k dielectric layer may include porous dielectric materials including silicon oxycarbide (SiOC); paragraph [0025]).
The instant specification identifies silicon oxycarbide (SiOC) as an example of the recited ultra-low dielectric constant dielectric material (describing the dielectric layer as including ULK dielectric materials such as a dielectric material with a dielectric constant less than four, preferably 2 to 3.5, and identifying porous dielectric materials such as silicon oxycarbide (SiOC) as examples; instant specification, paragraph [0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify modified Hineman to include wherein the dielectric layer comprises an ultra-low dielectric constant dielectric material, as taught by Wang, because Wang teaches using an ultra low-k dielectric layer surrounding MTJs in an MRAM device and further teaches silicon oxycarbide (SiOC) as an example porous dielectric material for the ultra low-k dielectric layer. Selecting Wang’s ultra low-k dielectric material for the dielectric layer of modified Hineman would have been the use of a known dielectric material in a similar MRAM dielectric structure to obtain the predictable result of providing low dielectric constant insulation around MTJ structures. See MPEP § 2141, subsection III(C).
Conclusion
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/JONATHAN L CARTER/Examiner, Art Unit 1713
/ERIN F BERGNER/Primary Examiner, Art Unit 1713
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