DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7-10, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20210175343 A1) herein after “Chen”.
Regarding claim 1, Figs. 7, 10, and 12 of Chen disclose a method for fabricating high electron mobility transistor (HEMT) (“a method for fabricating a HEMT”, ¶ [0009]), comprising:
forming a barrier layer (Fig. 7, first barrier layer 46, ¶ [0024]) on a substrate (Fig. 7, substrate 42, ¶ [0022]) (“a first barrier layer 46 is formed on the surface of the buffer layer 44”, ¶ [0024]);
forming a p-type semiconductor layer (Fig. 7, p-type semiconductor layer 48, ¶ [0025]) on the barrier layer (46) (“a p-type semiconductor layer 48 is formed on the surface of the first barrier layer 46”, ¶ [0025]);
forming a first hard mask (Fig. 10, hard mask 54, ¶ [0030]) on the p-type semiconductor layer (48) (“a hard mask 54 is formed to cover the second barrier layer 52”, ¶ [0030]), wherein the first hard mask (54) comprises metal oxide (“the hard mask 54 could include… aluminum oxide (AlO)”, ¶ [0030]); and
forming a passivation layer (Fig. 12, passivation layer 56, ¶ [0032]) on the first hard mask (54) (“a passivation layer 56 is formed on the surface of the hard mask 54”, ¶ [0032]).
Regarding claim 2, Figs. 7, 10, and 12 of Chen disclose the method of claim 1 as applied above, and Fig. 7 of Chen further discloses comprising forming a buffer layer (Fig. 7, buffer layer 44, ¶ [0023]) on the substrate (42) before forming the first barrier layer (46) (“a buffer layer 44 is formed on the substrate [42]”, ¶ [0023]).
Regarding claim 7, Figs. 7, 10, and 12 of Chen disclose the method of claim 1 as applied above, and Fig. 7 of Chen further discloses wherein the first hard mask (54) comprises aluminum oxide (AlO) (“the hard mask 54 could include… aluminum oxide (AlO)”, ¶ [0030]).
Regarding claim 8, Figs. 7, 10, and 12 of Chen disclose the method of claim 1 as applied above, and Fig. 7 of Chen further discloses wherein the barrier layer (46) comprise AlxGa1-xN (“the first barrier layer 46 is preferably made of III-V semiconductor such as aluminum gallium nitride (Al.sub.xGa.sub.1-xN)”, ¶ [0024]).
Regarding claim 9, Fig. 12 of Chen discloses a high electron mobility transistor (HEMT), comprising:
a barrier layer (46) on a substrate (42);
a p-type semiconductor layer (48) on the barrier layer (46);
a first hard mask (54) around the p-type semiconductor layer (48), wherein the first hard mask (54) comprises metal oxide; and
a passivation layer (56) on the first hard mask (54).
Regarding claim 10, Fig. 12 of Chen discloses the HEMT of claim 9 as applied above, and Fig. 12 of Chen further discloses comprising a buffer layer (44) between the substrate (42) and the barrier layer (46).
Regarding claim 14, Fig. 12 of Chen discloses the HEMT of claim 9 as applied above, and Fig. 12 of Chen further discloses wherein the first hard mask (54) comprises aluminum oxide (AlO) (“the hard mask 54 could include… aluminum oxide (AlO)”, ¶ [0030]).
Regarding claim 15, Fig. 12 of Chen discloses the HEMT of claim 9 as applied above, and Fig. 12 of Chen further discloses wherein the barrier layer (46) comprise AlxGa1-xN (“the first barrier layer 46 is preferably made of III-V semiconductor such as aluminum gallium nitride (Al.sub.xGa.sub.1-xN)”, ¶ [0024]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 9, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210013334 A1) herein after “Huang” in view of Lin et al. (US 20250338535 A1) herein after “Lin”.
Regarding claim 1, Figs. 1-3 of Huang disclose a method for fabricating high electron mobility transistor (HEMT), comprising:
forming a barrier layer (Fig. 1, barrier layer 16, ¶ [0010]) on a substrate (Fig. 1, substrate 12, ¶ [0008]) (“a barrier layer 16 is formed on the surface of the buffer layer 14”, ¶ [0010]);
forming a p-type semiconductor layer (Fig. 2, doped region 26, ¶ [0011]) on the barrier layer (16) (Fig. 2, “forms a doped region 26 in the barrier layer 16 and the buffer layer 14”, ¶ [0011]);
forming a first hard mask (Fig. 3, dielectric layer 30, ¶ [0013]) on the p-type semiconductor layer (26), wherein the first hard mask (30) comprises metal oxide (“the gate dielectric layer 30 is preferably made of… aluminum oxide (Al.sub.2O.sub.3)”, ¶ [0013]).
Huang discloses forming a dielectric layer (Fig. 6, IMD layers 38, ¶ [0016]) on the first hard mask (30), but fails to explicitly disclose that the dielectric layer is a passivation layer.
In the similar field of endeavor of high electron mobility transistors, Fig. 10 of Lin discloses forming a passivation layer (Fig. 10, third passivation layer 550, ¶ [0045]) on the first hard mask (Fig. 10, passivation layer 530, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Huang with the passivation layer as disclosed by Lin, to obtain the desired sheet resistance (see Lin, ¶ [0047]).
Regarding claim 3, Huang and Lin together disclose the method of claim 1 as applied above, and Figs. 1-4 of Huang further disclose comprising:
forming a second hard mask (Fig. 1, hard mask 18, ¶ [0011]) on the p-type semiconductor layer (26);
patterning the second hard mask (18) and the p-type semiconductor layer (26) (Fig. 2, “an etching process is conducted by using the patterned mask 20 as mask to remove part of the hard mask 18 and part of the barrier layer 16 to form a trench 28, in which the etching process only removes part of the doped region 26”, ¶ [0012]);
forming a third hard mask (Fig. 1, patterned mask 20, ¶ [0011]) on the p-type semiconductor layer (26);
stripping the third hard mask (Fig. 3, “an etching process is conducted by using the patterned mask 20”, ¶ [0012]);
forming the first hard mask (30) (Fig. 3, “a gate dielectric layer 30 is formed on the hard mask 18”, ¶ [0013]);
forming a gate electrode (32) on the second hard mask (18) (Fig. 4, “a gate electrode 32 is formed in the trench 28”, ¶ [0014]); and
forming a source electrode (34) and a drain electrode (36) adjacent to two sides of the gate electrode (32) (Fig. 4, “a source electrode 34 and a drain electrode 36 are formed in the two trenches adjacent to two sides of the gate electrode 32”, ¶ [0014]).
Huang discloses forming the dielectric layer (38) after forming the first hard mask layer (30), but fails to explicitly disclose that the dielectric layer is a passivation layer.
In the similar field of endeavor of high electron mobility transistors, Fig. 10 of Lin discloses forming the passivation layer (Fig. 10, “a third passivation layer 550 may be further formed”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Huang with the passivation layer as disclosed by Lin, to obtain the desired sheet resistance (see Lin, ¶ [0047]).
Regarding claim 4, Huang and Lin together disclose the method of claim 3 as applied above, and Huang further discloses wherein the first hard mask (30) and the second hard mask (18) comprise different material (“the hard mask 18 and the gate dielectric layer 30 are preferably made of different materials”, ¶ [0018]).
Regarding claim 5, Huang and Lin together disclose the method of claim 3 as applied above, but Huang fails to disclose wherein the second hard mask comprises metal nitride.
In the similar field of endeavor of high electron mobility transistors, Fig. 7 of Lin discloses wherein the second hard mask (Fig. 7, second passivation layer 540, ¶ [0038]) comprises metal nitride (“The second passivation layer 540 may include, for example… aluminum nitride”, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Huang with the second hard mask as disclosed by Lin, to provide insulation (see Lin, ¶ [0038]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 9, Fig. 6 of Huang discloses high electron mobility transistor (HEMT), comprising:
a barrier layer (16) on a substrate (12);
a p-type semiconductor layer (26) on the barrier layer (16);
a first hard mask (30) around the p-type semiconductor layer (26), wherein the first hard mask (30) comprises metal oxide.
Huang discloses a dielectric layer (38) on the first hard mask layer (30), but fails to explicitly disclose that the dielectric layer is a passivation layer.
In the similar field of endeavor of high electron mobility transistors, Fig. 7 of Lin discloses a passivation layer (550) on the first hard mask (530).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Huang with the passivation layer as disclosed by Lin, to obtain the desired sheet resistance (see Lin, ¶ [0047]).
Regarding claim 11, Huang and Lin together disclose the HEMT of claim 9 as applied above, and Fig. 6 of Huang further discloses comprising:
a second hard mask (18) on the p-type semiconductor layer (26);
a gate electrode (32) on the second hard mask (18); and
a source electrode (34) and a drain electrode (36) adjacent to two sides of the gate electrode (32).
Regarding claim 12, Huang and Lin together disclose the HEMT of claim 11 as applied above, and Fig. 6 of Huang further discloses wherein the first hard mask (30) and the second hard mask (18) comprise different material (“the hard mask 18 and the gate dielectric layer 30 are preferably made of different materials”, ¶ [0018]).
Regarding claim 13, Huang and Lin together disclose the HEMT of claim 11 as applied above, but Huang fails to disclose wherein the second hard mask comprises metal nitride.
In the similar field of endeavor of high electron mobility transistors, Fig. 7 of Lin discloses wherein the second hard mask (540) comprises metal nitride (“The second passivation layer 540 may include, for example… aluminum nitride”, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Huang with the second hard mask as disclosed by Lin, to provide insulation (see Lin, ¶ [0038]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210013334 A1) herein after “Huang334” and Lin (US 20250338535 A1) in further view of Huang et al. (US 20200111802 A1) herein after “Huang802”.
Regarding claim 6, Huang334 and Lin together disclose the method of claim 3 as applied above, but the combination fails to explicitly disclose wherein the first hard mask and the third hard mask comprise same material.
In the similar field of endeavor of transistor devices, Figs. 5 and 7 of Huang802 disclose the first hard mask (Fig. 7, third hard mask 48, ¶ [0027]) and the third hard mask (Fig. 5, second hard mask 38, ¶ [0023]) comprise same material (“The second hard mask 38 is preferably silicon oxide”, “the third hard mask 48 may be silicon oxide”, ¶ [0023] and [0027]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Huang334 with the hard mask materials as disclosed by Huang802, to obtain the desired insulating properties (see Huang802, ¶ [0027]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20200243675 A1) herein after “Liu” in view of Lin (US 20250338535 A1).
Regarding claim 16, Fig. 1A of Liu discloses a high electron mobility transistor (HEMT) (Fig. 1A, semiconductor structure 1, ¶ [0013]), comprising:
a buffer layer (Fig. 1A, buffer layer 19, ¶ [0013]) on a substrate (Fig. 1A, substrate 10, ¶ [0013]);
a barrier layer (Fig. 1A, first III-V compound layer 13, ¶ [0013]) on the buffer layer (19);
a hard mask (Fig. 1A, first passivation layer 17, ¶ [0013]) on the barrier layer (13),
a passivation layer (Fig. 1A, second passivation layer 18, ¶ [0013]) on the hard mask (17);
a gate electrode (Fig. 1A, gate region 16, ¶ [0021]) in the hard mask (17) and the passivation layer (18); and
a source electrode (Fig. 1A, source region 14, ¶ [0013]) and a drain electrode (Fig. 1A, drain region 15, ¶ [0013]) adjacent to two sides of the gate electrode (16).
Liu fails to disclose the hard mask comprises a metal oxide.
In the similar field of endeavor of high electron mobility transistors, Fig. 10 of Lin discloses wherein the hard mask (530) comprises a metal oxide (“The first passivation layer 530 may include, for example… aluminum oxide (AlO.sub.x)”, ¶ [0035]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Huang with the hard mask as disclosed by Lin, to provide insulation (see Lin, ¶ [0038]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 17, Liu and Lin together disclose the HEMT of claim 16 as applied above, and Fig. 1A of Liu further discloses wherein the gate electrode (16) contacts the barrier layer (13) directly (Fig. 1A, “The gate region 16 is on the first III-V compound layer 13”, ¶ [0021]).
Regarding claim 18, Liu and Lin together disclose the HEMT of claim 16 as applied above, but Liu fails to disclose wherein the hard mask comprises aluminum oxide (AlO).
In the similar field of endeavor of high electron mobility transistors, Fig. 10 of Lin discloses wherein the hard mask (530) comprises aluminum oxide (“The first passivation layer 530 may include, for example… aluminum oxide (AlO.sub.x)”, ¶ [0035]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Huang with the hard mask as disclosed by Lin, to provide insulation (see Lin, ¶ [0038]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 19, Liu and Lin together disclose the HEMT of claim 16 as applied above, and Fig. 1A of Liu further discloses wherein the barrier layer (13) comprise AlxGa1-xN (“the first III-V compound layer 13 includes an aluminum gallium nitride (AlGaN) layer”, ¶ [0018]).
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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