DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-11) in the reply filed on 07/17/2026 is acknowledged.
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/17/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2020/0266335) in view of Sung (US 2017/0222128).
Regarding claim 1, Wang discloses a semiconductor device, comprising :a substrate (Fig.7, numeral 12) defining a memory region (14), wherein the memory region has a boundary (Fig. 7, boundary between (14) and (16)); a dielectric layer (72) disposed on a memory cell (38), wherein a top surface of the dielectric layer (72) is higher than a top surface of a memory cell (38); and a trench (Fig.7, numeral 98) disposed in the dielectric layer (72), wherein the trench (98) is located between a memory cells closest to the boundary and the boundary (Fig.7); and the trench comprises an asymmetrical profile (98).
Wang does not disclose a plurality of memory cells disposed in the memory region.
Sung however discloses a plurality of memory cells disposed in the memory region (Fig.9, numeral 100A).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Wang with Sung to have a plurality of memory cells disposed in the memory region for the purpose of fabrication a MRAM cell region (Sung, [0043]).
Regarding claim 2, Wang discloses wherein in a cross-sectional view of the semiconductor device, the trench (98) comprises a V-shape (Fig.7).
Regarding claim 3, Wang discloses wherein in a cross-sectional view of the semiconductor device, the trench (98) comprises a first sidewall and a second sidewall disposed oppositely, and the first sidewall and the second sidewall are asymmetrical to each other (Fig.7).
Regarding claim 4, Wang discloses wherein in the cross-sectional view of the semiconductor device, the first sidewall is closer to the one of the plurality of memory cells (38) closest to the boundary than the second sidewall, the first sidewall comprises a concave curve, and the second sidewall comprises a convex curve (Fig.7, numeral 98).
Regarding claim 5, Wang discloses wherein in the cross-sectional view of the semiconductor device, the first sidewall (98) is closer to the one of the plurality of memory cells (38) closest to the boundary than the second sidewall, and an inclined degree of the first sidewall is smaller than an inclined degree of the second sidewall (Fig.7).
Regarding claim 7, Wang discloses wherein one of the plurality of memory cells has a height HH in a vertical direction, a distance SD is between a side (92) of the trench (98) adjacent to the boundary and the one of the plurality of memory cells (38) closest to the boundary in a horizontal direction, and the following condition is satisfied: 0 < SD ≤ 2HH ([0023]; Fig. 7; note: the thickness of (92) is smaller than the height of (38)).
Regarding claim 8, Wang does not wherein one of the plurality of memory cells has a height HH in a vertical direction, a distance SD is between a side of the trench adjacent to the boundary and the one of the plurality of memory cells closest to the boundary in a horizontal direction, and the following conditions are satisfied: 1600 Å ≤ HH≤1750 Å; and 120 nm ≤SD ≤350 nm.
It would have been however obvious to adjust a distance SD is between a side of the trench adjacent to the boundary and the one of the plurality of memory cells closest to the boundary in a horizontal direction to be in the claimed range for the purpose of optimization of barrier properties of metal interconnection (Wang, [0023]).
Regarding claim 9, Sung discloses a contact via (Fig. 15a, numeral 123’) formed in the dielectric layer (127), wherein the contact via exposes at least one of the plurality of memory cells (133); and a contact structure disposed in the contact via (123’) and electrically connected with the at least one of the plurality of memory cells (133).
Regarding claim 10, Wang discloses a metal layer (Fig.7, numeral 94) disposed in the trench (98), wherein a top surface of the metal layer (94) is aligned with a top surface of the contact structure (124).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Sung as applied to claim 1 above, and further in view of Kuo (US 2022/0216395).
Regarding claim 6, Wang does not disclose wherein in a top view of the semiconductor device, the trench has an annular shape and surrounds the plurality of memory cells.
Kuo however discloses wherein in a top view of the semiconductor device, the trench (Fig.1, numeral 26) has an annular shape and surrounds the plurality of memory cells (24).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Wang with Kuo to have in a top view of the semiconductor device, the trench has an annular shape and surrounds the plurality of memory cells for the purpose of preventing direct contact of dummy patterns with an array region (Kuo, [0012]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Sung as applied to claim 1 above, and further in view of KR’203 (KR 10-2003-0095203, cited in IDS, Machine Translation is provided).
Regarding claim 1, Wang does not disclose wherein the one of the plurality of memory cells closest to the boundary is a dummy memory cell.
KR’203 however discloses wherein the one of the plurality of memory cells closest to the boundary is a dummy memory cell (DMC).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Wang with KR’203 to have the one of the plurality of memory cells closest to the boundary is a dummy memory cell for the purpose of improving fabrication of memory cell rows (KR’203, Abstract).
Conclusion
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/JULIA SLUTSKER/ Primary Examiner, Art Unit 2891
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