DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 4 recites the limitation “the patterned photoresist layer” and “the pattern hard mask layer” in line 2. There is insufficient antecedent basis for these limitations in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 16-17, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KWON (Pub. No.: US 2021/0005807 A1).
Regarding claim 1, KWON discloses A method of fabricating magnetoresistive random-access memory (MRAM) cells on a substrate (substrate 100) that is formed with a bottom electrode layer (electrode layer 130), and a magnetic tunneling junction (MTJ) layer (MTJ layer 170) over the bottom electrode layer (see Fig. 1 and [0014], [0018], [0067]), said method comprising: forming a plurality of top electrode features (plurality of preliminary upper electrodes 185) over the MTJ layer (when using implementation of forming a plurality of memory units) (see Figs. 6-7 and [0036-0041], [0067]); performing a trimming process (fifth etching process) on the top electrode features, the MTJ layer and the bottom electrode layer to form a plurality of bottom electrodes (plurality of electrodes 135), a plurality of MTJ stacks (plurality of MTJ structures 175) respectively over the bottom electrodes (when using implementation of forming a plurality of memory units) (see Figs. 7-8 and [0045-0049], [0067]), and a plurality of top electrodes (plurality of electrodes 187) respectively over the MTJ stacks (see Fig. 8 and [0048-0056], [0067]); wherein each of the top electrodes is dome-shaped (plurality of electrodes 187 having protruding portion 187c being a dome-shape) (see Fig. 8).
Regarding claim 2, KWON discloses the method of Claim 1, wherein the trimming process is performed using ion bombardment (ion beam etching) (see Figs. 7-8 and [0045-0047]).
Regarding claim 4, KWON discloses the method of Claim 1, wherein etching of the top electrode layer is performed with the patterned photoresist layer (photoresist pattern) being disposed on top of the patterned hard mask layer (mask layer 210) (see Fig. 2 and [0025]).
Regarding claim 16, KWON discloses a method of fabricating memory cells on a substrate (substrate 100), comprising: forming a bottom electrode layer (electrode layer 130) over the substrate (see Fig. 1 and [0014], [0018]); forming a memory feature layer (MTJ layer 170) over the bottom electrode layer (see Fig. 1 and [0014], [0018]); forming a top electrode layer (electrode layer 180) over the memory feature layer (see Fig. 1 and [0018-0019]); patterning the top electrode layer, thereby forming a plurality of top electrodes (plurality of electrodes 187) (when using implementation of forming a plurality of memory units) (see Fig. 8 and [0048-0056], [0067]); and etching the memory feature layer and the bottom electrode layer with the top electrode layer thus patterned being disposed over the memory feature layer (fifth etching process) (see Figs. 7-8 and [0045-0049], [0067]); wherein the top electrodes are formed into a dome shape (plurality of electrodes 187 having protruding portion 187c being a dome-shape) during the etching of the memory feature layer and the bottom electrode layer (see Fig. 8 and [0048-0056]).
Regarding claim 17, KWON discloses the method of Claim 16, wherein the top electrodes have a flat top surface (top surfaces of the plurality of preliminary upper electrodes 185/top surfaces of electrodes 187) before the etching of the memory feature layer and the bottom electrode layer (see Figs. 6-7 and [0036-0044]).
Regarding claim 19, KWON discloses a method of fabricating memory cells on a substrate (substrate 100), comprising: forming a bottom electrode layer (electrode layer 130) over the substrate (see Fig. 1 and [0014], [0018]); forming a memory feature layer (MTJ layer 170) over the bottom electrode layer (see Fig. 1 and [0014], [0018]); forming a plurality of top electrode pillars (plurality of preliminary upper electrodes 185) over the memory feature layer when using implementation of forming a plurality of memory units) (see Figs. 6-7 and [0036-0041], [0067]); performing ion bombardment (fifth etching process include ion beam etching) to form the top electrode pillars, the memory feature layer and the bottom electrode layer into the memory cells, each of which includes a top electrode (one electrode 187) that corresponds to a respective one of the top electrode pillars, a bottom electrode (one electrode 135) that was a part of the bottom electrode layer, and a memory feature (one MTJ structure 175) that is disposed between the top electrode and the bottom electrode and that was a part of the memory feature layer (when using implementation of forming a plurality of memory units) (see Figs. 7-8 and [0045-0049], [0067]); wherein the top electrodes of the memory cells are dome-shaped (plurality of electrodes 187 having protruding portion 187c being a dome-shape) (see Fig. 8 and [0048-0056]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over KWON (Pub. No.: US 2021/0005807 A1) as applied to claim 1 above, and further in view of Wang et al. (Pub. No.: US 2020/0176510 A1), hereinafter as Wang.
Regarding claim 3, KWON discloses the method of Claim 1, thereby forming a patterned hard mask layer (second mask 230) (see Fig. 3 and [0028-0030]); and etching a top electrode layer (electrode layer 180) with the patterned hard mask layer being disposed on top of the top electrode layer, thereby forming the top electrode features (plurality of preliminary electrodes 85) (see Fig. 4 and [0032], [0067]). However, KWON fails to disclose wherein the forming of the top electrode features includes: forming a top electrode layer over the MTJ layer; forming a hard mask layer over the top electrode layer; forming a patterned photoresist layer over the hard mask layer; and etching the hard mask layer with the patterned photoresist layer serving as an etching mask,
Wang discloses a method of fabricating MRAM cells comprising forming a top electrode features includes forming a top electrode layer (metal layer 160) over a MTJ layer (MTJ layer 150) (see Fig. 5 and [0021]); forming a hard mask layer (hard mask layer 180) over the top electrode layer (see Fig. 6 and [0022]); forming a patterned photoresist layer (photoresist pattern 190) over the hard mask layer (see Fig. 6 and [0022]); and etching the hard mask layer with the patterned photoresist layer serving as an etching mask, thereby forming a patterned hard mask layer (180a) (see Fig. 7 and [0023]); and etching the top electrode layer with the patterned hard mask layer being disposed on top of the top electrode layer, thereby forming the top electrode features (top electrodes 160a) (see Figs. 7-8 and [0024-0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the method of forming the patterned photoresist layer into the method of KWON for etching the hard mask layer to form a patterned hard mask layer because the modified method would reduce manufacturing cost by reducing one extra step of depositing sacrificial material and extra mask.
Allowable Subject Matter
Claims 5-14, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Performing reactive ion etching (RIE) to remove by-products that were generated during the trimming process as recited in claim 5. Claims 6-15 depend on claim 5, and therefore also include said claimed limitation.
performing reactive ion etching (RIE) to remove by-products that were generated during the etching of the memory feature layer and the bottom electrode layer as recited in claim 18.
wherein the memory feature of each of the memory cells includes a first functional layer disposed over the bottom electrode, a second functional layer, and a third functional layer disposed between the second functional layer and the top electrode, wherein the second functional layer is made of a different material compared to the first functional layer and the third functional layer; and wherein the first functional layer has a sidewall surface that extends upward and inward, followed by upward and outward, starting from the bottom electrode to the second functional layer as recited in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818