DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (101; Fig 6; [0127]) = (element 101; Figure No. 6; Paragraph No. [0127]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 17 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by by LU; Hongting et al. (US 20230133179 A1) hereinafter Lu’179;
Regarding claim 17, Lu’179 teaches adisplay device (40; Fig 12; [0183]); comprising (see the entire document, fig 12, along with other relevant figures, specifically as cited below):
a substrate (101; Fig 5A, 6; [0127]); and
a plurality of sub-pixels (100; [0140]) disposed on the substrate (101), each of the plurality of sub-pixels (100) includes:
a pixel circuit layer ([0053]) disposed on the substrate, the pixel circuit layer having a sub-pixel circuit of each of the plurality of sub-pixels; and
a light emitting element layer(120; Fig 1A; [0066]) disposed on the pixel circuit layer, the light emitting element layer having a light emitting element of each of the plurality of sub-pixels,
wherein the pixel circuit layer includes:
a semiconductor layer (102; Fig6 ; [0132]);
a gate insulating layer (T1gT1G301; [0153]) disposed on the semiconductor layer;
a gate electrode layer (T1g-T7g; Fig 6; [0132]) disposed on the gate insulating layer;
an interlayer insulating layer (304) disposed on the gate electrode layer, the interlayer insulating layer including a first contact portion; and
a first metal layer (CA; Fig [0144]) disposed on the interlayer insulating layer, the first metal layer being directly connected to the gate electrode layer (T1g) through the first contact portion (CA), the first metal layer constituting a capacitor (Cst comprising {CA, CB}; Fig 7A, 7B; Fig 5B; [0144]) included in the sub-pixel circuit.
Allowable Subject Matter
Claims 1-16 are allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding independent claim 1. the references of the Prior Art of record in attached “PTO-892” and considered pertinent to the applicant's disclosure in searches and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: a sub-pixel, comprising, inter alia, “a first capacitor including a first electrode connected to the first power line and a second electrode connected to the second node, wherein the second electrode is directly connected to the gate electrode of the first transistor, a semiconductor layer of the third transistor, and a semiconductor layer of the fourth transistor” as recited in Claim 1.
The benefits of these novel features, as further disclosed by the instant specification in paragraphs [0010]-[0019], [0150], [0176]. by increasing capacitance with structuring the first capacitor so its second electrode is directly connected to multiple circuit parts, including the first transistor gate connection and the semiconductor layers of the third and fourth transistors [0007]. In described embodiments, the capacitor is extended across multiple metal layers and connected through contact/via structures, which increases effective electrode area without enlarging the pixel footprint.
The most relevant prior arts of references Lu’179 discloses substantially the features of the claims 1 and 18 as follows.
Lu’179 discloses a sub-pixel (sub-pixel; Fig 1A; [0050,0114]) comprising:
a light emitting element (120; [0066]);
a first transistor (T1; Fig 3A; [0083]) connected between a first power line and a first node, the first transistor including a gate electrode connected to a second node;
a second transistor (T2; Fig 3A; [0085]) connected to a data line, the second transistor including a gate electrode connected to a first sub-gate line, the second transistor receiving a data signal supplied from the data line in response to a first scan signal supplied from the first sub-gate line;
a third transistor (T3; Fig 3A; [0086]) including a gate electrode connected to a third sub-gate line, the third transistor switching electrical connection between the first node and the second node in response to a third scan signal supplied from the third sub-gate line;
a fourth transistor (T4; Fig 3A; [0088]) including a gate electrode connected to a second sub-gate line, the fourth transistor switching electrical connection between the second node and a third power line in response to a second scan signal supplied from the second sub-gate line;
a fifth transistor (T5; Fig 3A; [0090]) including a gate electrode connected to an emission control line, the fifth transistor switching electrical connection between the first node and the light emitting element in response to an emission control signal supplied from the emission control line;
Because no reference alone, nor is there any motivation to combine the details over the prior art to create such limitations in the independent claim 1 is deemed patentable over the prior arts.
Regarding claim 2-16, these are allowed because these inherit the allowable subject matter from claim 1.
Claims 18-20 would be allowable if rewritten to include all of the limitations of base claim 17,
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, either singularly or in combination, does not disclose or suggest “the capacitor including a first electrode connected to the first power line and a second electrode connected to the second node, wherein the second electrode is directly connected to the gate electrode of the first transistor, a semiconductor layer of the third transistor, and a semiconductor layer of the fourth transistor” For this reason, claim 18 is found to contain allowable subject matter.
Claims 19-20 depend on claim 18, and thus also contains the same allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
July 8, 2026
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