DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered.
Election/Restrictions
Applicant’s election without traverse of Group II, species ‘a’ in the reply filed on 1/13/26 is acknowledged. Applicant has amended the claims and points to claims 10, 15-17 and 21-30 as readable thereon.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10, 15-17, 21-24 and 30-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morishima (US 2006/0023555).
Regarding claim 10, Morishima discloses a method, comprising: during a first standby period (see claim 4-5), providing a first control signal (see Figure 13, PEC) having a first voltage level to a bit line pre-charger (see Figure 5, BPCG DPCG); adjusting the first control signal to a second voltage level different from the first voltage level to activate the bit line pre-charger (see Figure 15 for example, PEC toggled); and when the bit line pre-charger is activated, charging at least one bit line by the bit line pre- charger (see claims 4-5).
Regarding claim 15, Morishima discloses the method of claim 10, further comprising: during the first standby period, toggling the first control signal between the first voltage level and the second voltage level (see Figure 15 in view of claim 4-5 during standby PEC is toggled to precharge).
Regarding claim 16, Morishima discloses the method of claim 15, further comprising: generating the first control signal according to an enable signal (BS) and a clock signal (ICLK, see Figure 13); and during the first standby period, toggling the clock signal and maintaining the enable signal at the first voltage level (see Figure 15 in view of paragraphs 0160-161).
Regarding claim 17, Morishima discloses the method of claim 16, wherein generating the first control signal comprises: receiving each of the clock signal and the enable signal by a logic element (116)
Regarding claim 21, Morishima discloses a method, comprising: providing a first control signal (PEC) having a first voltage level (inactive level) to a bit line pre-charger; during a first standby period, toggling the first control signal (see claim 4); adjusting the first control signal to a second voltage level (active level) different from the first voltage level to activate the bit line pre-charger (DPCG, BPCG charge data/bit lines according to PEC); and when the bit line pre-charger is activated, charging at least one bit line by the bit line pre- charger (see claim 4).
Regarding claim 22, Morishima discloses the method of claim 21, wherein toggling the first control signal comprises: toggling the first control signal between the first voltage level and the second voltage level (inactive to active and/or vice versa).
Regarding claim 23, Morishima discloses the method of claim 22, further comprising: generating the first control signal according to an enable signal and a first clock signal; and during the first standby period, toggling the first clock signal and maintaining the enable signal at the first voltage level (see Figure 11 and 13).
Regarding claim 24, Morishima discloses the method of claim 23, wherein generating the first control signal comprises: receiving each of the first clock signal and the enable signal by a first logic element (116).
Claims 30 and 31 recite substantially the same features as above and are rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marishima.
Regarding claim 25, Morishima discloses the method of claim 24, but the first logic element is a NAND logic gate. However, the use of NAND logic gates for such signal logic combinations is well-known and understood in the art. Therefore, it would have been obvious to one having ordinary skill at the time of filing to use a NAND logic gate as the first logic element since the use of NAND gates for clock gating circuits was common and well-known at the time of filing and would yield the predictable result of NAND operations producing the output signal.
Allowable Subject Matter
Claims 26-29 and 32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 26 and 32, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including: outputting a second control signal by a second logic element; and generating the first control signal based on the second control signal, wherein a first input terminal of the second logic element is coupled to an output terminal of the first logic element.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The remaining cited and attached references teach various embodiments of bit line precharge and standby configurations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS KING/Primary Examiner, Art Unit 2824