Prosecution Insights
Last updated: July 17, 2026
Application No. 18/756,147

DISPLAY DEVICE

Non-Final OA §102§103§112
Filed
Jun 27, 2024
Priority
Jul 06, 2023 — RE 10-2023-0087723
Examiner
TIVARUS, CRISTIAN ALEXANDRU
Art Unit
Tech Center
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
33 granted / 43 resolved
+16.7% vs TC avg
Strong +22% interview lift
Without
With
+22.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
33 currently pending
Career history
88
Total Applications
across all art units

Statute-Specific Performance

§103
90.0%
+50.0% vs TC avg
§102
6.0%
-34.0% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 43 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The prior art documents submitted by applicant in the Information Disclosure Statement filed on 06/27/2024 has been considered and made of record. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites the limitation: “wherein a distance between any two adjacent openings among the plurality of openings is greater than a distance between two other openings”. The “two other openings” may also be adjacent, in which case the distance between them cannot be greater the distance between any other adjacent openings. Paragraph [0012] of the written description recites: “a distance between any two adjacent openings among the openings may be greater than a distance between two other openings”. For the purpose of examination, claim 5 will be interpreted as: The display device of claim 1, wherein a distance between any two adjacent openings among the openings may be greater than a distance between two other openings. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3-5, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al., (United States Patent US 10,770,681 B2), hereinafter referenced as Lee. Regarding claim 1, Lee teaches a display device comprising: a display area (Fig.1, area DA) and a non-display area (Fig.1, area PA, surrounding the display area); a light emitting element layer disposed on a substrate in the display area (Fig.2, element #130 disposed on the substrate, element #110) and comprising a pixel electrode (Fig.2, element #131), an organic light emitting layer (Fig.2, element #133) and a common electrode (Fig.1, element #135); a circuit part disposed on the substrate in the non-display area and comprising a plurality of circuit transistors (Fig.2, circuit part formed by the circuits in the non-display area, including transistors TFT2 and element #170); and a pixel defining layer extending from the display area to the circuit part (Fig.2, element #119), wherein the pixel defining layer comprises a plurality of openings overlapping the circuit part, and the plurality of openings do not overlap the plurality of circuit transistors (Fig.2, only the openings in element #119 located to the right side of the rightmost transistor TFT2). Regarding claim 3, Lee teaches the display device of claim 1 as set forth in the anticipation rejection. Lee further teaches the display device of claim 1, wherein ones of the plurality of circuit transistors that do not overlap the openings among the plurality of circuit transistors overlap the pixel defining layer (Fig.2, elements #TFT2 overlap parts of element #119, vertical lines from the source or drain of the transistors will intersect element #119, which means they overlap from top view). Regarding claim 4, Lee teaches the display device of claim 1 as set forth in the anticipation rejection. Lee teaches the display device of claim 1, wherein a distance between any two adjacent openings among the plurality of openings varies (Fig.2, the pixel definition layer between the openings located at the right side of the rightmost transistor, has dome shapes, which means the horizontal distance between two openings varies as a function of height). Regarding claim 5, Lee teaches the display device of claim 1 as set forth in the anticipation rejection. Lee teaches the display device of claim 1, wherein a distance between any two adjacent openings among the plurality of openings may be greater than a distance between two other openings (Fig.1, distance W1 is greater than the distance between two adjacent opening in the vertical direction). Regarding claim 7, Lee teaches the display device of claim 1 as set forth in the anticipation rejection. Lee further teaches the display device of claim 1, further comprising: a via layer disposed on the display area and the non-display area and disposed between the substrate and the pixel defining layer (Fig.2, element #118), wherein the plurality of openings expose an upper surface of the via layer (Fig.2, the upper surface of the right most element #118 is exposed by the opening). Regarding claim 8, Lee teaches the display device of claim 1 as set forth in the anticipation rejection. Lee teaches the display device of claim 1, wherein the common electrode extends from the display area to the circuit part and overlaps at least some of the plurality of circuit transistors (Fig.2, element #135 extends from DA to PA and overlaps transistors TFT2). Claims 9-14 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhou et al., (United States Patent Application Publication Number, US 2025/0268045 A1), hereinafter referenced as Zhou. Regarding claim 9, Zhou teaches a display device comprising: a display area (Fig.3, element #100) and a non-display area (fig.2, element #301 and #302); a light emitting element layer disposed on a substrate in the display area (Fig.3, formed by elements #21, #24 and #25, disposed on substrate, element #10) and comprising a pixel electrode (Fig.3, element #21), an organic light emitting layer (Fig.3, element #24), and a common electrode (Fig.3, element #25); a plurality of circuit parts disposed on the substrate in the non-display area and comprising a plurality of circuit transistors (Fig.3, elements #301A, #301B and #301C, and transistors #201, #202 and #203, the device has multiple rows each having transistors); and a pixel defining layer extending from the display area to the plurality of circuit parts (Fig.3, element #22), wherein the common electrode extends from the display area to the circuit parts (Fig.3, element #25 extends from display area #100 to circuit part #301), the pixel defining layer comprises a plurality of openings overlapping the plurality of circuit parts (Fig.3, only the plurality of openings of element #22 located in regions #301A and #301B), some of the plurality of circuit transistors overlap the common electrode (Fig.3, transistors elements #201 and #202 completely overlap element #25), the plurality of openings overlap at least some of the plurality of circuit transistors that overlap the common electrode (Fig.3, plurality of openings of element #22 located in regions #301A and #301B overlap transistors #201 and #202), and the plurality of openings do not overlap any of the plurality of circuit transistors that do not overlap the common electrode (Fig.3, plurality of openings of element #22 located in regions #301A and #301B do not overlap transistors #203, which do not completely overlap element #25). Regarding claim 10, Zhou teaches the display device of claim 9 as set forth in the anticipation rejection. Zhou teaches the display device of claim 9, wherein the plurality of circuit parts comprise a first circuit part disposed adjacent to the display area (Fig.3, element #301A is adjacent to element #100) and a second circuit part spaced farther apart from the display area than the first circuit part (Fig.3, formed by element #301B and #301C), the first circuit part comprises a plurality of first circuit transistors (Fig.3, element #201), and the common electrode overlaps each of the plurality of first circuit transistors (Fig.3, element #25 overlaps elements #201). Regarding claim 11, Zhou teaches the display device of claims 9 and 10 as set forth in the anticipation rejection. Zhou teaches the display device of claim 10, wherein the second circuit part comprises (2-1)th circuit transistors adjacent to the first circuit part (Fig.3, elements #202) and (2-2)th circuit transistors disposed between an outer side of the substrate and the (2-1)th circuit transistors (Fig.3, elements #203), and the common electrode overlaps the (2-1)th circuit transistors and does not overlap the (2-2)th circuit transistors (Fig.3, element #25 completely overlaps elements #202 and does not completely overlap elements #203). Regarding claim 12, Zhou teaches the display device of claims 9, 10 and 11 as set forth in the anticipation rejection. Zhou teaches the display device of claim 11, wherein the plurality of openings overlap at least some of the first circuit transistors and at least some of the (2-1)-th circuit transistors (Fig.3, plurality of openings of element #22 located in regions #301A and #301B overlap transistors #201 and #202). Regarding claim 13, Zhou teaches the display device of claims 9, 10, 11 and 12 as set forth in the anticipation rejection. Zhou teaches the display device of claim 12, wherein the openings do not overlap any of the (2-2)th circuit transistors (Fig.3, plurality of openings of element #22 located in regions #301A and #301B do not overlap transistors #203). Regarding claim 14, Zhou teaches a display device comprising: a display area (Fig.5, element #100) and a non-display area (Fig.5, element #300); a light emitting element layer disposed on a substrate in the display area (Fig.5, formed by elements #21, #24 and #25, disposed on substrate, element #10) and comprising a pixel electrode (Fig.5, element #21), an organic light emitting layer (Fig.5, element #24), and a common electrode (Fig.5, element #25); a plurality of circuit parts disposed on the substrate in the non-display area and comprising a plurality of circuit transistors (Fig.5, elements #301A, #301B and #301C, and transistors #201, #202 and #203, the device has multiple rows each having transistors); and a pixel defining layer extending from the display area to the plurality of circuit parts (Fig.5, element #22), and comprising a plurality of openings overlapping the plurality of circuit parts (Fig.3, only the plurality of openings of element #22 located in regions #301A and #301B), wherein the plurality of openings overlap some of the plurality of circuit transistors (Fig.3, plurality of openings of element #22 located in regions #301A and #301B overlap transistors #201 and #202), and do not overlap the other circuit transistors (Fig.3, the plurality of openings of element #22 located in regions #301A and #301B do not overlap transistors #203). Regarding claim 20, Zhou teaches the display device of claim 14 as set forth in the anticipation rejection. Zhou teaches the display device of claim 14, further comprising a thin-film encapsulation layer disposed on the light emitting element layer and extending from the display area to the non-display area, wherein the thin-film encapsulation layer overlaps the plurality of circuit transistors (Fig.5, element #23). Claims 14, 18 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al., (United States Patent Application Publication Number, US 2018/0033830 A1), hereinafter referenced as Kim. Regarding claim 14, Kim teaches a display device comprising: a display area (Fig.13A, element DA) and a non-display area (Fig.13A, element NDA); a light emitting element layer disposed on a substrate in the display area (Fig.13A, element OLED disposed on substrate element SUB) and comprising a pixel electrode (Fig.13A, element AE), an organic light emitting layer (Fig.13A, element EML) and a common electrode (Fig.13a, element CE); a plurality of circuit parts disposed on the substrate in the non-display area and comprising a plurality of circuit transistors (Fig.13A, circuit parts comprise transistors T6, GDL_T, each row comprise of these transistors); and a pixel defining layer extending from the display area to the plurality of circuit parts (Fig.13A, element PDL) and comprising a plurality of openings overlapping the plurality of circuit parts (Fig.13A, element PDL has a plurality of openings overlapping the non-display area NDA where the plurality of circuit parts are located), wherein the plurality of openings overlap some of the plurality of circuit transistors and do not overlap the other circuit transistors (Fig.13A, the openings overlap transistors GDL_T and do not overlap T6). Regarding claim 18, Kim teaches the display device of claim 14 as set forth in the anticipation rejection. Kim teaches the display device of claim 14, wherein the plurality of circuit transistors comprise an oxide semiconductor (Fig.6C, OSP1 and OSAP2 may be oxide semiconductors, paragraph [0090], rows 9-11) . Regarding claim 19, Kim teaches the display device of claim 14 as set forth in the anticipation rejection. Kim teaches the display device of claim 14, further comprising: a via layer disposed between the substrate and the pixel defining layer and covering the plurality of circuit transistors (Fig.13A, element #30); and a connection line disposed between the pixel defining layer and the via layer and overlapping the plurality of circuit transistors (Fig.13A, element E-CNT). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Ahn et al., (United States Patent Application Publication Number, US 2015/0041765 A1) hereinafter referenced as Ahn. Regarding claim 2, Lee teaches the display device of claim 1 as set forth in the anticipation rejection. Lee teaches wherein the pixel defining layer covers edges of the pixel electrode (Fig.2, element #119 covers edges of element #131). Lee does not teach the display device of claim 1, wherein the pixel defining layer comprises a black pigment or dye. Ahn teaches wherein the pixel defining layer comprises a black pigment or dye (Fig.1, element #370, paragraph [0079], rows 10-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ahn and disclose the pixel defining layer comprises a black pigment or dye. As disclosed by Ahn, when the pixel defining layer comprise a black pigment it may serve as a light blocking member (paragraph [0079], rows 10-13), which absorbs light and therefore reduce glare. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Cho et al., (United States Patent Application Publication Number, US 2019/0165079 A1) hereinafter referenced as Cho. Regarding claim 6, Lee teaches the display device of claim 1 as set forth in the anticipation rejection. Lee teaches the display device of claim 1, wherein the plurality of circuit transistors comprise silicon or an organic semiconductor material (column 4, row 36-42). Lee does not teach wherein the plurality of circuit transistors comprise an oxide semiconductor. Cho teaches does not teach wherein the plurality of circuit transistors comprise silicon or an oxide semiconductor (Fig.5, transistor TRd, paragraph [0065], rows 109). Thus, both references, Lee and Cho, teach transistors in the non-display area used to control and drive signals applied to the display area. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the transistor disclosed by Lee which comprise silicon or an organic semiconductor could have been replaced for the transistor disclosed by Cho which comprises silicon or an oxide semiconductor because both serve the same purpose of providing a transistor in the non-display area used to control and drive signals applied to the display area. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing transistors in the non-display area used to control and drive signals applied to the display area. Oxide semiconductors have high electron mobility and optical transparency, which makes them ideal for transparent display applications. Allowable Subject Matter Claim 15 is allowed if written in independent form. Claims 16 and 17 are allowed as being dependent on claim 15. The following is a statement of reasons for the indication of allowable subject matter. Regarding claim 15, the cited prior art does not teach or fairly suggests, along with other claimed features: “and the plurality of buffer transistors of each of the first and second circuit parts do not overlap any of the plurality of openings.” Yao et al., (United States Patent Application Number, US 2022/0068212 A1) teaches wherein the plurality of circuit parts comprise a first circuit part disposed adjacent to the display area (Fig.1A, element #104) and a second circuit part spaced farther apart from the display area than the first circuit part (Fig.1A, element #105), each of the first circuit part and the second circuit part comprises a plurality of buffer transistors (Fig 1C, element #105 has buffer transistors T9 and T10, Fig.1F, element #104 has buffer transistors T24 and T25). Yao does not teach the plurality of buffer transistors of each of the first and second circuit parts do not overlap any of the plurality of openings. Kim et al., (United States Patent Application Number, US 2018/0033830 A1) teaches wherein the plurality of circuit parts comprise a first circuit part disposed adjacent to the display area (Fig.13A, circuit part comprising transistor T6 and multiple rows) and a second circuit part spaced farther apart from the display area than the first circuit part (Fig.13A, circuit part comprising transistor GDL_T and multiple rows), each of the first circuit part and the second circuit part comprises a plurality of buffer transistors (Fig.6A, T6 of each row is a buffer transistor in the first circuit part, T5 of each row is a buffer transistor in the second circuit part) and T6 is not covered by the openings . Kim does not teach the plurality of buffer transistors of second circuit parts do not overlap any of the plurality of openings. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM -5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Jun 27, 2024
Application Filed
Jul 08, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+22.3%)
3y 5m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 43 resolved cases by this examiner. Grant probability derived from career allowance rate.

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