DETAILED ACTION
This action is responsive to the application No. 18/756,313 filed on June 27, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
This Office action is responsive to the application 18/756,313 filed on 06/27/2024. Accordingly, pending in this Office action are claims 1-20.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12-14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fang (US 2019/0006408).
Regarding Claim 12, Fang (see, e.g., Figs. 1A-1I), teaches a method for forming a semiconductor device, comprising:
forming a trench 118 in a substrate 110 between a first photodiode 116 and a second photodiode 116 (see, e.g., Fig. 1D, pars. 0026-0027);
forming a barrier layer 160 in the trench 118 (see, e.g., Fig. 1E, par. 0036);
forming a copper layer 180 over the barrier layer 160 in the trench 118 (see, e.g., Fig. 1G, pars. 0044-0046);
removing a portion of the copper layer 180 to expose the barrier layer 160 (see, e.g., Fig. 1H, par. 0046); and
forming a first dielectric layer 190 over the copper layer 180 after removing the portion of the copper layer 180, the first dielectric layer 190 directly contacting the barrier layer 160 (see, e.g., Fig. 1I, par. 0051).
Regarding Claim 13, Fang teaches all aspects of claim 12. Fang (see, e.g., Figs. 1A-1I), teaches, forming a color filter layer 210 over the first dielectric layer 190 (see, e.g., Fig. 1I, par. 0052).
Regarding Claim 14, Fang teaches all aspects of claim 13. Fang (see, e.g., Figs. 1A-1I), teaches, forming a lens array 220 over the color filter layer 210 (see, e.g., Fig. 1I, par. 0053).
Regarding Claim 16, Fang teaches all aspects of claim 12. Fang (see, e.g., Figs. 1A-1I), teaches, forming a second dielectric layer 170 over the barrier layer 160 in the trench 118 prior to forming the copper layer 180 (see, e.g., Fig. 1G, par. 0042).
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (US 2020/0006410).
Regarding Claim 17, Wu (see, e.g., Figs. 1-12), teaches a method for forming a semiconductor device, comprising:
recessing a first portion of a substrate 24 overlying a photodiode 26 to form a tapered sidewall 56A (see, e.g., Fig. 3, pars. 0019, 0026-0027);
forming a first dielectric layer 62 overlying the tapered sidewall 56A (see, e.g., Fig. 5, par. 0031);
removing a first portion of the first dielectric layer 62 and a second portion of the substrate 24 to define a trench 64 (see, e.g., Fig. 6, par. 0032); and
forming a deep trench isolation (DTI) structure 70 in the trench 64 such that the DTI structure 70 is within the substrate 24 and the first dielectric layer 62 and adjacent the photodiode 26 (see, e.g., Fig. 9, par. 0037).
Regarding Claim 18, Wu teaches all aspects of claim 17. Wu (see, e.g., Figs. 1-12), teaches that forming the DTI structure 70 comprises:
forming a second dielectric layer 66 in the trench 64 (see, e.g., Fig. 7, par. 0033); and
forming a copper layer 68 over the second dielectric layer 66 in the trench 64 (see, e.g., Fig. 8, par. 0034).
Regarding Claim 19, Wu teaches all aspects of claim 17. Wu (see, e.g., Figs. 1-12), teaches forming a second dielectric layer 72 over the DTI structure 70 and directly contacting the first dielectric layer 62 (see, e.g., Fig. 10, par. 0038).
Regarding Claim 20, Wu teaches all aspects of claim 19. Wu (see, e.g., Figs. 1-12), teaches forming a color filter layer 74 over the second dielectric layer 72 (see, e.g., Fig. 11, par. 0041).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmed (US 2015/0279878) in view of Borthakur (US 2020/0021754).
Regarding Claim 1, Ahmed (see, e.g., Figs. 7A-7D), teaches a method for forming a semiconductor device, comprising:
forming a first dielectric layer 93 over a substrate 41 (see, e.g., pars. 0036, 0059);
forming a trench 45 extending through the first dielectric layer 93 and into the substrate 41 (see, e.g., pars. 0037, 0059);
forming a barrier layer 51 over the first dielectric layer 93 and in the trench 45 (see, e.g., par. 0037);
forming a second dielectric layer 49 over the barrier layer 51 and in the trench 45 (see, e.g., par. 0037); and
forming a layer 47 over the second dielectric layer 49 and in the trench 45 (see, e.g., par. 0039).
Ahmed does not teach that the layer is a copper layer.
Ahmed discloses the claimed invention except for the use of a doped polysilicon layer instead of a copper layer. Borthakur (see, e.g., par. 0023), in similar deep trench isolation structures to Ahmed, on the other hand, teaches that copper and doped polysilicon are equivalent materials known in the art. Therefore, because these conductive materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute copper for doped polysilicon since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Regarding Claim 7, Ahmed and Borthakur teach all aspects of claim 1. Ahmed (see, e.g., Figs. 7A-7D), teaches planarizing to expose a top surface of the first dielectric layer 93 after forming the copper layer (see, e.g., par. 0063).
Regarding Claim 9, Ahmed and Borthakur teach all aspects of claim 7. Ahmed (see, e.g., Figs. 7A-7D), teaches that the planarizing further exposes the second dielectric layer 49 and the barrier layer 51 (see, e.g., par. 0063).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ahmed (US 2015/0279878) in view of Borthakur (US 2020/0021754) and further in view of Chen (US 6,290,833).
Regarding Claim 2, Ahmed and Borthakur teach all aspects of claim 1. They are silent with respect to the claim limitation that forming the copper layer comprises performing a plating process with a current density of at least about 5 milli-amperes per square centimeter.
Chen (see, e.g., Abstract), on the other hand, teaches forming a copper layer by performing a plating process which provides an excellent conformal copper coating that fills trenches, vias, and other microstructures having good uniformity, low sheet resistance and are readily annealed at low temperatures.
It would have been obvious to one of ordinary skill in the art at the time of filing to form the copper layer in Ahmed’s/Borthakur’s device by a plating process, as taught by Chen, to provide an excellent conformal copper coating that fills trenches, vias, and other microstructures having good uniformity, low sheet resistance and are readily annealed at low temperatures.
Chen is silent with respect to the claim limitation that the plating process is performed with a current density of at least about 5 milli-amperes per square centimeter.
However, this claim limitation is merely considered a change in the current density in the electroplating process of Chen’s method. The specific claimed current density, absent any criticality, is only considered to be an obvious modification of the current density of Chen’s process, as the courts have held that changes in current density without any criticality, are within the level of skill in the art. According to the courts, a particular current density is nothing more than one among numerous current densities that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed current density, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed current density in Chen’s process.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed current density or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen current density or upon another variable recited in a claim, the applicant must show that the chosen current density is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 3-6, 8, 10, 11, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/Primary Examiner, Art Unit 2814
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