DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/27/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 20 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the hardmask layer" in line 1. There is insufficient antecedent basis for this limitation in the claim because there is no previous mention of a hardmask layer in claims 1 and 10. For examination purposes, “the hardmask layer” is being interpreted as “a hardmask layer.” Appropriate correction is required.
Claim 20 recites the limitation "the inner spacer" in line 3. There is insufficient antecedent basis for this limitation in the claim because there is no previous mention of an inner spacer in claims 17 or 20. For examination purposes, claim 20 is being interpreted as being dependent on claim 18 to have proper antecedence for the inner spacer. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 5-10, 12-13, 16 and 18-20 of U.S. Patent No. 12,051,733. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 11 and 17 are broader than, and anticipated by claims 1, 10 and 18 pf patent no. 12,051,733. Claims 2-10, 12-16 and 18-20 are also similar and anticipated by claims 2, 5-9, 12-13, 16 and 19-20 of patent no. 12,051,733. See the table below for claim to claim comparisons.
Current Application
Patent No. 12,051,733
1. A method for making a semiconductor device, comprising: forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another; forming a dummy gate structure over the fin structure and extending along a second direction perpendicular to the first direction; and forming a gate spacer extending in the second direction along respective upper sidewall portions of the dummy gate structure and separated by a portion of the dummy gate structure from a topmost one of the plurality of channel layers, such that a first distance between a bottom surface of the gate spacer and a top surface of the topmost one of the plurality of channel layers is defined by the portion of the dummy gate structure.2. The method of claim 1, wherein the first distance is similar to a second distance that separates neighboring ones of the plurality of channel layers.
1. A method for making a semiconductor device, comprising: forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another; forming a dummy gate structure, over the fin structure, that extends along a second direction perpendicular to the first direction; and forming a gate spacer extending in the second direction along respective upper sidewall portions of the dummy gate structure and separated by a portion of the dummy gate structure from a topmost one of the plurality of channel layers, thereby defining a first distance between a bottom surface of the gate spacer and a top surface of the topmost one of the plurality of channel layers by the portion of the dummy gate structure; wherein the first distance is similar to a second distance that separates neighboring ones of the plurality of channel layers.
3. The method of claim 2, wherein the second distance is equal to a thickness of each of the plurality of sacrificial layers.
2. The method of claim 1, wherein the second distance is equal to a thickness of each of the plurality of sacrificial layers.
4. The method of claim 1, wherein forming the fin structure further comprises overlaying the fin structure with a hardmask layer.
5. The method of claim 1, wherein the step of forming a fin structure further comprises overlaying the fin structure with a hardmask layer, and wherein the hardmask layer and the dummy gate structure include a similar material.
5. The method of claim 4, wherein the hardmask layer and the dummy gate structure include a similar material.
5. The method of claim 1, wherein the step of forming a fin structure further comprises overlaying the fin structure with a hardmask layer, and wherein the hardmask layer and the dummy gate structure include a similar material.
6. The method of claim 4, further comprising: retaining the hardmask layer while forming the dummy gate structure; and subsequently to forming the dummy gate structure, recessing portions of the hardmask layer that are not overlaid by the dummy gate structure such that the first distance is defined by a thickness of a remaining portion of the hardmask layer.
6. The method of claim 5, further comprising: retaining the hardmask layer while forming the dummy gate structure; and subsequently to forming the dummy gate structure, recessing portions of the hardmask layer that are not overlaid by the dummy gate structure such that the first distance is defined by a thickness of a remaining portion of the hardmask layer.
7. The method of claim 4, further comprising removing the hardmask layer prior to forming the dummy gate structure such that the first distance is defined by a thickness of a lower portion of the dummy gate structure.
7. The method of claim 5, further comprising removing the hardmask layer prior to forming the dummy gate structure such that the first distance is defined by a thickness of a lower portion of the dummy gate structure.
8. The method of claim 4, further comprising: retaining the hardmask layer while forming the dummy gate structure; forming a first layer of the dummy gate structure; recessing the hardmask layer and the first layer of the dummy gate structure at a similar etching rate, thereby forming a coplanar surface shared by the top surface of the topmost channel layer and a top surface of the first layer of the dummy gate structure; forming a second layer of the dummy gate structure; and replacing respective sidewall portions of the second layer of the dummy gate structure with the gate spacer.
8. The method of claim 5, further comprising: retaining the hardmask layer while forming the dummy gate structure; forming a first layer of the dummy gate structure; recessing the hardmask layer and the first layer of the dummy gate structure at a similar etching rate, thereby forming a coplanar surface shared by the top surface of the topmost channel layer and a top surface of the first layer of the dummy gate structure; forming a second layer of the dummy gate structure; and replacing respective sidewall portions of the second layer of the dummy gate structure with the gate spacer.
9. The method of claim 4, further comprising: retaining the hardmask layer while forming the dummy gate structure; forming a first layer of the dummy gate structure; recessing the hardmask layer and the first layer of the dummy gate structure at different etching rates, thereby causing a top surface of the topmost channel layer to be below a top surface of the first layer of the dummy gate structure; forming a second layer of the dummy gate structure; and replacing respective sidewall portions of the second layer of the dummy gate structure with the gate spacer.
9. The method of claim 5, further comprising: retaining the hardmask layer while forming the dummy gate structure; forming a first layer of the dummy gate structure; recessing the hardmask layer and the first layer of the dummy gate structure at different etching rates, thereby causing a top surface of the topmost channel layer to be below a top surface of the first layer of the dummy gate structure; forming a second layer of the dummy gate structure; and replacing respective sidewall portions of the second layer of the dummy gate structure with the gate spacer.
10. The method of claim 1, wherein the hardmask layer and the dummy gate structure include a similar material.
5. The method of claim 1, wherein the step of forming a fin structure further comprises overlaying the fin structure with a hardmask layer, and wherein the hardmask layer and the dummy gate structure include a similar material.
11. A method for making a semiconductor device, comprising: forming a fin structure extending along a first direction and comprising a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another; and forming a gate spacer extending along sidewalls of a patterned upper layer of a dummy gate structure, wherein the upper layer extends along a second direction perpendicular to the first direction, wherein the dummy gate structure is formed over a hardmask layer that is disposed over the fin structure, and wherein a thickness of a remaining portion of the hardmask layer is about equal to a distance separating neighboring ones of the plurality of channel layers.13. The method of claim 11, wherein the gate spacer is in contact with a topmost one of the plurality of channel layers.
14. The method of claim 11, wherein the gate spacer is separated from a topmost one of the plurality of channel layers.
10. A method for making a semiconductor device, comprising: forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another; and forming a gate spacer that extends along sidewalls of a patterned upper layer of a dummy gate structure, wherein the upper layer extends along a second direction perpendicular to the first direction, wherein the dummy gate structure is formed over a hardmask layer that is disposed over the fin structure, and wherein a thickness of a remaining portion of the hardmask layer is about equal to a distance separating neighboring ones of the plurality of channel layers; wherein the gate spacer is either in contact with or separated from a topmost one of the plurality of channel layers.
12. The method of claim 11, wherein the hardmask layer and the dummy gate structure include a similar material.
16. The method of claim 10, wherein the hardmask layer and the dummy gate structure include a similar material.
15. The method of claim 11, wherein forming the gate spacer further comprises: removing the hardmask layer; forming the dummy gate structure comprising a blanket upper layer and a blanket lower layer over the fin structure; etching the blanket upper layer to form the patterned upper layer; and forming the gate spacer such that the gate spacer is separated from the topmost channel layer with a remaining portion of the blanket lower layer or a remaining portion of the patterned upper layer.
12. The method of claim 10, wherein the step of forming a gate spacer further comprises: removing the hardmask layer; forming the dummy gate structure that comprises a blanket upper layer and a blanket lower layer over the fin structure; etching the blanket upper layer to form the patterned upper layer; and forming the gate spacer such that the gate spacer is separated from the topmost channel layer with a remaining portion of the blanket lower layer and/or a remaining portion of the patterned upper layer.
16. The method of claim 15, wherein a thickness of the remaining portion of the blanket lower layer or the remaining portion of the patterned upper layer is about equal to a distance separating neighboring ones of the plurality of channel layers.
13. The method of claim 12, wherein a thickness of the remaining portion of the blanket lower layer or the remaining portion of the patterned upper layer is about equal to a distance separating neighboring ones of the plurality of channel layers.
17. A semiconductor device, comprising: a plurality of channel layers over a substrate, wherein the plurality of channel layers laterally extend along a first direction and are vertically separated from each other; a dummy gate structure that extends along a second direction perpendicular to the first direction and wraps around each of the plurality of channel layers; and a gate spacer that extends along upper sidewalls of the dummy gate structure along the second direction, wherein the gate spacer is separated from a topmost channel layer of the plurality of channel layers by a portion of the dummy gate structure.
18. The semiconductor device of claim 17, further comprising an inner spacer that is disposed below the gate spacer and between neighboring ones of the plurality of channel layers.
18. A semiconductor device, comprising: a plurality of channel layers over a substrate, wherein the plurality of channel layers laterally extend along a first direction and are vertically separated from each other; a dummy gate structure that extends along a second direction perpendicular to the first direction and wraps around each of the plurality of channel layers; a gate spacer that extends along upper sidewalls of the dummy gate structure along the second direction; and an inner spacer that is disposed below the gate spacer and between neighboring ones of the plurality of channel layers; wherein the gate spacer is separated from a topmost channel layer of the plurality of channel layers by a portion of the dummy gate structure.
19. The semiconductor device of claim 17, wherein a distance between a bottom surface of the gate spacer and a top surface of the topmost channel layer is about equal to a distance separating the neighboring ones of the plurality of channel layers.
19. The semiconductor device of claim 18, wherein a distance between a bottom surface of the gate spacer and a top surface of the topmost channel layer is about equal to a distance separating the neighboring ones of the plurality of channel layers
20. The semiconductor device of claim 17, wherein the distance separating the neighboring ones of the plurality of channel layers is equal to a thickness of each portion the inner spacer that is between neighboring ones of the plurality of channel layers.
20. The semiconductor device of claim 18, wherein the distance separating the neighboring ones of the plurality of channel layers is equal to a thickness of each portion the inner spacer that is between neighboring ones of the plurality of channel layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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