DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/27/2024, has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the horizontal through via structure must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 19 is objected to because of the following informalities:
Claim 19, line 1 should read “The structure of Claim 16”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it is unclear how the “frontside back-end-of-line (BEOL) structure” is “located on the frontside of the FEOL level” and the “backside BEOL structure” is additionally located “on the frontside of the FEOL level.” This goes against the known definitions of the terms of art “frontside” and “backside,” which require location of the BEOL structures on opposing sides of the FEOL level, and the claimed structure is indefinite by dictating both frontside and backside structures located to the same side of the FEOL.
For the purposes of examination, it will be interpreted that the claim should read “a frontside back-end-of-line (BEOL) structure located on the frontside of the FEOL level: a backside BEOL located on the backside of the FEOL level,” as supported by at least paragraph 0033 and Figure 1.
Claims 2-7 are rejected as inheriting the deficiencies of claim 1.
Claims 2-6, 9-13, and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, it is unclear whether the claim limitation “or any combination thereof” is meant to modify the phrase “comprises (i) an increase…, (ii) ILD materials…, or (iii) metal conductors…,” meaning any combination of either (i), (ii), or (iii), or if “any combination thereof” is meant to modify solely the options present in (iii), i.e. metal conductors in either the frontside BEOL structure or the backside BEOL structure and ILD materials in either the frontside BEOL structure or the backside structure, for instance: the metal conductor frontside and ILD frontside, the metal conductor frontside and ILD backside, the metal conductor backside and ILD frontside, or the metal conductor backside and ILD backside. The specification of the application does not provide clarification of this distinction and only provides duplicate recitation of the claim language.
For purposes of examination, it will be interpreted that the phrase “any combination thereof” modifies options (i), (ii), and (iii).
Claims 3-6 are rejected as inheriting the deficiencies of claim 2.
Claims 9 and 16 are rejected for the same reason given in the rejection of claim 2 above.
Claims 10-13 are rejected as inheriting the deficiencies of claim 9.
Claims 17-20 are rejected as inheriting the deficiencies of claim 16.
Claims 4, 5, 11, 12, 18, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, it is unclear whether the claim limitation “the thermal conductivity of the ILD materials is from greater than 1W/mK to 10W/mk” is intended to mean 1W/mK < x < 10W/mK, where x refers to the thermal conductivity of the ILD materials, or if it refers to a value greater than 1-10WmK, i.e. x > 10W/mK, therefore the claim is rendered indefinite. The disclosure of the specification, which makes reference to a range from 0.5W/mK up to 2000W/mK fails to make clear which interpretation is intended. For the purposes of examination, it will be interpreted that the applicant intended a range 1W/mK < x < 10W/mK, where x refers to the thermal conductivity of the ILD materials.
Claims 11 and 18 are rejected as having the same deficiency and should be addressed accordingly.
Regarding claim 5, it is unclear whether the claim limitation “the thermal conductivity of the ILD materials is from greater than 10W/mK to 500W/mK” is intended to mean 10W/mK < x < 500W/mK, where x refers to the thermal conductivity of the ILD materials, or if it refers to a value greater than 10-500W/mK, i.e. x > 500W/mK, therefore the claim is rendered indefinite. . The disclosure of the specification, which makes reference to a range from 0.5W/mK up to 2000W/mK fails to make clear which interpretation is intended. For the purposes of examination, it will be interpreted that the applicant intended a range 10W/mK < x < 500W/mK, where x refers to the thermal conductivity of the ILD materials.
Claims 12 and 19 are rejected as having the same deficiency and should be addressed accordingly.
Claims 3, 10, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, it is unclear how the claim limitation “the percentage of metal structures present in at least one of the frontside BEOL structure or the backside BEOL structure is from 10% to greater than 50% of level needed for chiplet or chiplet stack function” is meant to be interpreted. It is unclear if this limitation would result in a range from 10% to infinity, or would result in a range including 10% and a further 50% to infinity. The specification of the instant application does not provide clarification regarding intended interpretation of this claim, and it is therefore indefinite. For purposes of examination, it will be interpreted that the claim limitation reads upon any percentage greater than 10%.
Claims 10 and 17 are rejected as having the same deficiency and should be addressed accordingly.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6, 8, 9, 11, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US PGPub 2021/0082784; herein known as Cheng).
Regarding claim 1, Cheng teaches (Fig. 5) a semiconductor structure comprising: a front-end-of-the-line (FEOL) level (104, [0018]) comprising at least one semiconductor device ([0018]) and having a frontside (top) and a backside (bottom); a frontside back-end-of-the-line (BEOL) structure (120, [0022]) located on the frontside of the FEOL level; a backside BEOL structure (116, [0022]) located on the frontside of the FEOL level; and a heat path (500, [0051]) in which heat is spread in a horizontal direction to edges of the structure, and then the heat that is spread to the edges is removed in a vertical direction.
Regarding claim 2, Cheng teaches the semiconductor structure of Claim 1, wherein the heat path comprises
(i) an increase of metal structures (118, [0029]) present at least one of the frontside BEOL structure or the backside BEOL structure to a percentage that is beyond that which is required by power delivery or signal delivery. Cheng teaches wherein conductive structures 122 of 118 are included for electrical conductivity ([0022]) and conductive structures 150 of 118 are included for thermal conductivity ([0029]).
(ii) ILD materials in at least one of the frontside BEOL structure or the backside BEOL structure that have a thermal conductivity greater than 0.5 W/mK up to 2000 W/mK ([0017]).
Regarding claim 4, Cheng teaches the semiconductor structure of Claim 2, wherein the heat path comprises (ii) or (iii) and the thermal conductivity of the ILD materials is from greater than 1 W/mK to 10 W/mK ([0017]).
Regarding claim 6, Cheng teaches (Fig. 5) the semiconductor structure of Claim 2, wherein at least a first set of metal structures (116, [0022]) present in at least one of the frontside BEOL structure (120, []) extend laterally to an edge of frontside BEOL structure. The metallization structures of 116 are shown to extend laterally in the direction of the edges of the first semiconductor chip.
Regarding claim 8, Cheng teaches (Fig. 5) a chip stack containing structure comprising: at least one row of a second semiconductor chip (104, [0022]) stacked above, and bonded to, a first semiconductor chip (102, [0022]); and a heat path (500, [0051]) in which heat is spread in a horizontal direction to edges of the at least one row of comprising the second semiconductor chip stacked above, and bonded to, the first semiconductor chip, and then the heat that is spread to the edges is removed in a vertical direction (See Figure).
Regarding claim 9, Cheng teaches (Fig. 5) the chip stack containing structure of Claim 8, wherein the heat path comprises
(i) an increase of metal structures (118, [0029]) present at least one of the first semiconductor chip or the second semiconductor chip to a percentage that is beyond that which is required by power delivery or signal delivery. Cheng teaches wherein conductive structures 122 of 118 are included for electrical conductivity ([0022]) and conductive structures 150 of 118 are included for thermal conductivity ([0029]).
(ii) ILD materials in the first semiconductor chip or the second semiconductor chip that have a thermal conductivity greater than 0.5 W/mK up to 2000 W/mK ([0017]).
Regarding claim 11, Cheng teaches (Fig. 5) the chip stack containing structure of Claim 9, wherein the heat path comprises (ii) and the thermal conductivity of the ILD materials is from greater than 1 W/mK to 10 W/mK ([0017]).
Regarding claim 13, Cheng teaches (Fig. 5) the chip stack containing structure of Claim 9, wherein a first set of metal structures (116, [0022]) present in the first semiconductor chip (102, [0022]) extends laterally to an edge of the first semiconductor chip. The metallization structures of 116 are shown to extend laterally in the direction of the edges of the first semiconductor chip.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 2 above.
Regarding claim 3, Cheng teaches The semiconductor structure of Claim 2, wherein the heat path comprises (i) but does not explicitly teach the percentage of metal structures present in at least one of the frontside BEOL structure or the backside BEOL structure is from 10% to greater than 50% of level needed for chiplet or chiplet stack function.
The instant application fails to teach criticality or an unexpected result of the claimed range, evidenced by order over which the claimed range falls (10% or any value over 50%).
Cheng teaches wherein the amount of conductive metal structures present in the semiconductor chip can be modified in order to increase heat dissipation from hot spots for efficient heat dissipation, as a result effective variable.
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Cheng in view of Kim to include wherein the heat path comprises (i) and the percentage of metal structures present in at least one of the frontside BEOL structure or the backside BEOL structure is from 10% to greater than 50% of level needed for chiplet or chiplet stack function in order to modify heat dissipation of the package.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 1 above, and further in view of Lear et al. (US PGPub 2023/0170275; herein known as Lear).
Regarding claim 7, Cheng teaches the semiconductor structure of Claim 1 and a through via structure (148A, [0028]) embedded in a through via dielectric region (132, [0031]) and extending from the backside BEOL structure (116) to the frontside BEOL structure (120), but does not explicitly teach further comprising a packaging substrate electrically connected to the backside BEOL structure and a lid attached to the frontside BEOL structure.
In analogous art, Lear teaches (Fig. 1C) a packaging substrate (202, [0076]) electrically connected to the backside BEOL structure (114-3) and a lid (128, [0059]) attached to the frontside BEOL structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng and of Lear to include a packaging substrate electrically connected to the backside BEOL structure and a lid attached to the frontside BEOL structure in order to provide protective packaging to the BEOL device ([0058]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 9 above.
Regarding claim 10, Cheng teaches the chip stack containing structure of Claim 9, wherein the heat path comprises (i) and the percentage of metal structures present in at least one of the first semiconductor chip or the second semiconductor chip is from 10% to greater than 50% of level needed for chiplet or chiplet stack function.
The instant application fails to teach criticality or an unexpected result of the claimed range, evidenced by order over which the claimed range falls (10% or any value over 50%).
Cheng teaches wherein the amount of conductive metal structures present in the semiconductor chip can be modified in order to increase heat dissipation from hot spots for efficient heat dissipation, as a result effective variable.
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Cheng to include wherein the heat path comprises (i) and wherein the percentage of metal structures present in the semiconductor chip is from 10% to greater than 50% of level needed for chiplet or chiplet stack function in order to modify heat dissipation of the package.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 9 above, and further in view of Yu et al. (US PGPub 2021/015920; herein known as Yu).
Regarding claim 12, Cheng teaches the chip stack containing structure of Claim 9, wherein the heat path comprises (ii) but does not explicitly teach the thermal conductivity of the ILD materials is from greater than 10 W/mK to 500 W/mK.
In analogous art, Yu teaches the thermal conductivity of the ILD materials is from greater than 10 W/mK to 500 W/mK ([0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng and of Yu to include the thermal conductivity of the ILD materials is from greater than 10 W/mK to 500 W/mK in order to improve heat dissipation performance of semiconductor dies ([0034]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 8 above, and further in view of Lear.
Regarding claim 14, Cheng teaches the chip stack containing structure of Claim 8, further comprising a through via structure (148A, [0028]) embedded in a through via dielectric region (132, [0031]) and extending vertically from the first semiconductor chip (102) to the second semiconductor chip (104) and a horizontal through via structure (142, [0031]) located on top of the at least one of the second semiconductor chip (104) stacked above, and bonded to, the first semiconductor chip (102). For purposes of examination, a horizontal through via structure is interpreted to be a horizontal conductive structure above and bonded to the first semiconductor chip. Cheng does not explicitly teach a packaging substrate electrically connected to the first semiconductor chip.
In analogous art, Lear teaches a packaging substrate (102, [0058]) electrically connected to the first semiconductor chip (112, [0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng and of Lear to include a packaging substrate electrically connected to the first semiconductor chip in order to allow for external connection to the semiconductor chip stack ([0058]).
Claims 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lear.
Regarding claim 15, Cheng teaches (Fig. 5) a structure comprising: a semiconductor chip (102, [0019]), wherein the semiconductor chip comprises a heat path (500, [0051]) in which heat is spread in a horizontal direction (x) to edges of the semiconductor chip, and then the heat that is spread to the edges is removed in a vertical direction (see 500 in Figure); and a dielectric material structure (132, [0025]) laterally adjacent to, and located on top of, the semiconductor chip, wherein the dielectric material structure comprises a core layer (140, [0017]) embedded therein.
Cheng does not explicitly teach a semiconductor chip electrically connected to a packaging substrate.
In analogous art, Lear teaches a packaging substrate (102, [0058]) electrically connected to the semiconductor chip (112, [0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng and of Lear to include a semiconductor chip electrically connected to a packaging substrate in order to allow for external connection to the semiconductor chip stack ([0058]).
Regarding claim 16, Cheng in view of Lear teaches (Cheng, Fig. 5) the structure of Claim 15, wherein the heat path comprises
(i) an increase of metal structures (118, [0029]) present at least one of the first semiconductor chip or the second semiconductor chip to a percentage that is beyond that which is required by power delivery or signal delivery. Cheng teaches wherein conductive structures 122 of 118 are included for electrical conductivity ([0022]) and conductive structures 150 of 118 are included for thermal conductivity ([0029])
(ii) ILD materials in the structure that have a thermal conductivity greater than 0.5 W/mK up to 2000 W/mK ([0017])
Regarding claim 17, Cheng in view of Lear teaches the structure of Claim 16, wherein the heat path comprises (i) but does not explicitly teach the percentage of metal structures present in the semiconductor chip is from 10% to greater than 50% of level needed for chiplet or chiplet stack function.
The instant application fails to teach criticality or an unexpected result of the claimed range, evidenced by order over which the claimed range falls (10% or any value over 50%).
Cheng teaches wherein the amount of conductive metal structures present in the semiconductor chip can be modified in order to increase heat dissipation from hot spots for efficient heat dissipation, as a result effective variable.
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Cheng in view of Lear to include wherein the heat path comprises (i) and wherein the percentage of metal structures present in the semiconductor chip is from 10% to greater than 50% of level needed for chiplet or chiplet stack function in order to modify heat dissipation of the package.
Regarding claim 18, Cheng in view of Lear teaches the structure of Claim 16, wherein the heat path comprises (ii) and the thermal conductivity of the ILD materials is from greater than 1 W/mK to 10 W/mK (Cheng, [0017])
Regarding claim 20, Cheng in view of Lear teaches (Cheng, Fig. 5) the structure of Claim 16, wherein a first set of metal structures (116, [0022]) present in the semiconductor chip (102, [0022]) extend laterally to an edge of the semiconductor chip. The metallization structures of 116 are shown to extend laterally in the direction of the edges of the first semiconductor chip.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lear as applied to claim 16 above, and further in view of Yu.
Regarding claim 19, Cheng in view of Lear teaches the chip stack containing structure of Claim 16, wherein the heat path comprises (ii) but does not explicitly teach the thermal conductivity of the ILD materials is from greater than 10 W/mK to 500 W/mK.
In analogous art, Yu teaches the thermal conductivity of the ILD materials is from greater than 10 W/mK to 500 W/mK ([0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng and of Yu to include the thermal conductivity of the ILD materials is from greater than 10 W/mK to 500 W/mK in order to improve heat dissipation performance of semiconductor dies ([0034]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
