DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group II in the reply filed on 2/11/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). More specifically, the Restriction Requirement of 12/18/25 contained two separate requirements: (1) a Restriction Requirement based on combination and subcombination of Groups I and II, and (2) a Species Election Requirement identifying two separate species. Applicant’s response only addresses the Species Election Requirement (with traverse, as discussed below) but cancels the claims of Group I (Claims 1-11) of the Restriction Requirement. Accordingly, the selection of Group II (Claims 17-20) of the Restriction Requirement is considered to be without traverse.
Applicant's election with traverse of Claims 12 and 14-20 in the reply filed on 2/11/26 is acknowledged. The traversal is on the ground that Species I and II identified in the Species Election Requirement of 12/18/25 are not mutually exclusive. Applicant’s argument is persuasive and therefore the Species Election Requirement of 12/18/25 is withdrawn.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Applicant is advised that this Double Patenting rejection will not be held in abeyance. See MPEP § 804(I)(B)(1); 37 CFR § 1.111(b).
Claims 12 and 14-32 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9, 12, and 15-19 of U.S. Patent No. 12,056,080. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the features of the instant claims can be found in the conflicting claims, and thus are anticipated by those claims.
Instant Claims
Conflicting Patent Claims
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC device through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period, wherein the first slave BMIC device is configured to: collect measurement data for a plurality of battery cells of the first battery pack; compress the measurement data into fewer data bits using a data compression method based on voltage differences among the plurality of battery cells; pack the compressed measurement data in a data frame; and send the data frame in a burst mode of transmission to the master BMIC device as a first Isolated SPI signal at the first Isolated SPI interface of the first slave BMIC device.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
18. The battery system of claim 15, wherein the BMIC device is configured to: collect, by the digital control circuit, outputs from the ADCs, wherein the outputs from the ADCs comprise measurements for the plurality of battery cells of the battery pack; compress, by the digital control circuit, the measurements for the plurality of battery cells into few data bits using a data compression method based on voltage differences among the plurality of battery cells; pack, by the digital control circuit, the compressed measurements for the plurality of battery cells in a data frame; and send, by the first interface circuit, the data frame in a burst mode of transmission as a first Isolated SPI signal.
14. The battery management system of claim 12, wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a second Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the second Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the second Isolated SPI signal to a second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the second Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending the measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as the first Isolated SPI signal.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
15. The battery management system of claim 14, wherein the first slave BMIC device is configured to relay the second Isolated SPI signal regardless of whether the ID number matches the device ID.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
16. The battery management system of claim 15, wherein the first slave BMIC device is configured to relay the second Isolated SPI signal while the first slave BMIC device processes the digital bits.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
17. A battery system comprising: a battery pack comprising a plurality of battery cells; and a battery management integrated circuit (BMIC) device coupled to the battery pack, the BMIC device comprising: a first plurality of input/output (I/O) pins; a first interface circuit coupled to the first plurality of I/O pins, wherein the first interface circuit comprises a first decoding circuit and a first format converter; a second plurality of I/O pins; a second interface circuit coupled to the second plurality of I/O pins, wherein the second interface circuit comprises a second decoding circuit and a second format converter; a first data bus coupled between outputs of the first decoding circuit and inputs of the second format converter; a second data bus coupled between outputs of the second decoding circuit and inputs of the first format converter; a digital control circuit coupled to the first data bus and the second data bus; and analog-to-digital converters (ADCs) coupled between the digital control circuit and the battery pack, wherein each of the first decoding circuit and the second decoding circuit is configured to decode an Isolated Serial Peripheral Interface (SPI) signal into a three-pin signal, wherein the Isolated SPI signal is a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period and an idle period following the bit period, wherein the three-pin signal includes a first data signal, a second data signal, and a synchronization signal, wherein each of the first format converter and the second format converter is configured to convert the three-pin signal into the Isolated SPI signal.
15. A battery system comprising: a battery pack comprising a plurality of battery cells; and a battery management integrated circuit (BMIC) device coupled to the batter pack, the BMIC device comprising: a first plurality of input/output (I/O) pins; a first interface circuit coupled to the first plurality of I/O pins, wherein the first interface circuit comprises a first decoding circuit and a first format converter; a second plurality of I/O pins; a second interface circuit coupled to the second plurality of I/O pins, wherein the second interface circuit comprises a second decoding circuit and a second format converter; a first data bus coupled between outputs of the first decoding circuit and inputs of the second format converter; a second data bus coupled between outputs of the second decoding circuit and inputs of the first format converter; a digital control circuit coupled to the first data bus and the second data bus; and analog-to-digital converters (ADCs) coupled between the digital control circuit and the battery pack, wherein each of the first decoding circuit and the second decoding circuit is configured to decode an Isolated Serial Peripheral Interface (SPI) signal into a three-pin signal, wherein the Isolated SPI signal is a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period and an idle period that have a same duration, wherein the three-pin signal includes a first data signal, a second data signal, and a synchronization signal, wherein each of the first format converter and the second format converter is configured to convert the three-pin signal into the Isolated SPI signal.
18. The battery system of claim 17, wherein during the bit period, the positive signal transitions from a positive value to a negative value, or vice versa, wherein in the idle period, the positive signal remains at a zero value, wherein the digital control circuit is configured to convert the three-pin signal into digital bits by sampling the first data signal of the three-pin signal at rising edges of the synchronization signal.
16. The battery system of claim 15, wherein in a bit frame of the positive signal, the idle period follows the bit period, wherein during the bit period, the positive signal transitions from a positive value to a negative value, or vice versa, wherein in the idle period, the positive signal remains at a zero value, wherein the digital control circuit is configured to convert the three-pin signal into digital bits by sampling the first data signal of the three-pin signal at rising edges of the synchronization signal.
19. The battery system of claim 18, wherein each of the first decoding circuit and the second decoding circuit is configured to decode the Isolated SPI signal by: generating a positive pulse in the first data signal if the bit frame carries a digital bit of one, or generating a positive pulse in the second data signal if the bit frame carries a digital bit of zero, wherein a rising edge of the positive pulse is generated before a start of the idle period of the bit frame, and a falling edge of the positive pulse is generated before an end of the idle period of the bit frame; and generating a positive synchronization pulse in the synchronization signal, wherein a rising edge of the positive synchronization pulse is between the rising edge and the falling edge of the positive pulse.
17. The battery system of claim 16, wherein for each bit frame of the Isolated SPI signal, each of the first decoding circuit and the second decoding circuit is configured to decode the Isolated SPI signal by: generating a positive pulse in the first data signal if the bit frame carries a digital bit of one, or generating a positive pulse in the second data signal if the bit frame carries a digital bit of zero, wherein a rising edge of the positive pulse is generated before a start of the idle period of the bit frame, and a falling edge of the positive pulse is generated before an end of the idle period of the bit frame; and generating a positive synchronization pulse in the synchronization signal, wherein a rising edge of the positive synchronization pulse is between the rising edge and the falling edge of the positive pulse in the first data signal or in the second data signal.
20. The battery system of claim 17, wherein the BMIC device is configured to: collect, by the digital control circuit, outputs from the ADCs, wherein the outputs from the ADCs comprise measurement data for the plurality of battery cells of the battery pack; compress, by the digital control circuit, the measurement data for the plurality of battery cells into fewer data bits using a data compression method based on voltage differences among the plurality of battery cells; pack, by the digital control circuit, the compressed measurement data into a data frame; and send, by the first interface circuit, the data frame as a first Isolated SPI signal.
18. The battery system of claim 15, wherein the BMIC device is configured to: collect, by the digital control circuit, outputs from the ADCs, wherein the outputs from the ADCs comprise measurements for the plurality of battery cells of the battery pack; compress, by the digital control circuit, the measurements for the plurality of battery cells into few data bits using a data compression method based on voltage differences among the plurality of battery cells; pack, by the digital control circuit, the compressed measurements for the plurality of battery cells in a data frame; and send, by the first interface circuit, the data frame in a burst mode of transmission as a first Isolated SPI signal.
21. The battery management system of claim 12, wherein during the bit period of the bit frame, the positive signal transitions from a positive value to a negative value, or vice versa, wherein in the idle period, the positive signal remains at a zero value.
19. The battery management system of claim 12, wherein during the bit period of the bit frame, the positive signal transitions between a positive value and a negative value, wherein during the idle period of the bit frame, the positive signal remains at a zero value.
22. The battery management system of claim 14, further comprising a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to the second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
23. The battery management system of claim 22, wherein the first slave BMIC device is further configured to: receive, at the second Isolated SPI interface of the first slave BMIC device, a third Isolated SPI signal from the second slave BMIC device; and relay the third Isolated SPI signal by outputting the third Isolated SPI signal at the first Isolated SPI interface of the first slave BMIC device.
9. The IC device of claim 8, wherein in the slave mode, the IC device is configured to: receive a third Isolated SPI signal at the first plurality of I/O pins; decode, by the first decoding circuit, the third Isolated SPI signal into the three-pin signal; convert, by the digital control circuit, the three-pin signal into digital bits; process, by the digital control circuit, the digital bits; and relay the third isolated SPI signal by outputting the third Isolated SPI signal at the second plurality of I/O pins.
24. The battery management system of claim 23, wherein the third Isolated SPI signal comprises measurement data of the second battery pack.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
9. The IC device of claim 8, wherein in the slave mode, the IC device is configured to: receive a third Isolated SPI signal at the first plurality of I/O pins; decode, by the first decoding circuit, the third Isolated SPI signal into the three-pin signal; convert, by the digital control circuit, the three-pin signal into digital bits; process, by the digital control circuit, the digital bits; and relay the third isolated SPI signal by outputting the third Isolated SPI signal at the second plurality of I/O pins.
25. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC device, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
26. The battery management system of claim 25, wherein the first slave BMIC device is configured to process the digital bits by: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface of the first slave BMIC device.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
27. The battery management system of claim 26, wherein the first battery pack comprises one or more battery cells, wherein the measurement data comprises measured voltages of the one or more battery cells, wherein the first slave BMIC device is configured to compress the measurement data into fewer data bits using a data compression method based on differences among the measured voltages.
18. The battery system of claim 15, wherein the BMIC device is configured to: collect, by the digital control circuit, outputs from the ADCs, wherein the outputs from the ADCs comprise measurements for the plurality of battery cells of the battery pack; compress, by the digital control circuit, the measurements for the plurality of battery cells into few data bits using a data compression method based on voltage differences among the plurality of battery cells; pack, by the digital control circuit, the compressed measurements for the plurality of battery cells in a data frame; and send, by the first interface circuit, the data frame in a burst mode of transmission as a first Isolated SPI signal.
28. The battery management system of claim 27, wherein the first slave BMIC device is configured to pack the compressed measurement data from the one or more battery cells into a data frame for transmission.
18. The battery system of claim 15, wherein the BMIC device is configured to: collect, by the digital control circuit, outputs from the ADCs, wherein the outputs from the ADCs comprise measurements for the plurality of battery cells of the battery pack; compress, by the digital control circuit, the measurements for the plurality of battery cells into few data bits using a data compression method based on voltage differences among the plurality of battery cells; pack, by the digital control circuit, the compressed measurements for the plurality of battery cells in a data frame; and send, by the first interface circuit, the data frame in a burst mode of transmission as a first Isolated SPI signal.
29. The battery management system of claim 26, wherein the first slave BMIC device is further configured to relay the first Isolated SPI signal to the second slave BMIC device through the second Isolated SPI interface of the first slave BMIC device regardless of whether the ID number matches the device ID.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
30. The battery management system of claim 25, wherein the first slave BMIC device is coupled to the master BMIC device through galvanic isolation, and the second slave BMIC device is coupled to the first slave BMIC device through galvanic isolation.
12. A battery management system comprising: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; a first slave BMIC device, wherein a first Isolated SPI interface of the first slave BMIC device is coupled to an Isolated SPI interface of the master BMIC through galvanic isolation, wherein the first slave BMIC device is configured to be coupled to a first battery pack, wherein the Isolated SPI interface is a two-pin communication interface using a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period followed by an idle period that has a same duration as the bit period; and a second slave BMIC device, wherein a first Isolated SPI interface of the second slave BMIC device is coupled to a second Isolated SPI interface of the first slave BMIC device through galvanic isolation, wherein the second slave BMIC device is configured to be coupled to a second battery pack; wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; relay, by the first slave BMIC device, the first Isolated SPI signal to the second Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits, comprising: comparing the ID number with a device ID of the first slave BMIC device; and in response to determining that the ID number matches the device ID, sending measurement data of the first battery pack to the master BMIC device through the first Isolated SPI interface as a second Isolated SPI signal.
31. The battery management system of claim 26, wherein during the bit period of the bit frame, the positive signal changes its value once from a positive value to a negative value, or vice versa, wherein in the idle period, the positive signal remains at a zero value.
16. The battery system of claim 15, wherein in a bit frame of the positive signal, the idle period follows the bit period, wherein during the bit period, the positive signal transitions from a positive value to a negative value, or vice versa, wherein in the idle period, the positive signal remains at a zero value, wherein the digital control circuit is configured to convert the three-pin signal into digital bits by sampling the first data signal of the three-pin signal at rising edges of the synchronization signal.
32. The battery management system of claim 31, wherein the bit period and the idle period have a same duration.
15. A battery system comprising: a battery pack comprising a plurality of battery cells; and a battery management integrated circuit (BMIC) device coupled to the batter pack, the BMIC device comprising: a first plurality of input/output (I/O) pins; a first interface circuit coupled to the first plurality of I/O pins, wherein the first interface circuit comprises a first decoding circuit and a first format converter; a second plurality of I/O pins; a second interface circuit coupled to the second plurality of I/O pins, wherein the second interface circuit comprises a second decoding circuit and a second format converter; a first data bus coupled between outputs of the first decoding circuit and inputs of the second format converter; a second data bus coupled between outputs of the second decoding circuit and inputs of the first format converter; a digital control circuit coupled to the first data bus and the second data bus; and analog-to-digital converters (ADCs) coupled between the digital control circuit and the battery pack, wherein each of the first decoding circuit and the second decoding circuit is configured to decode an Isolated Serial Peripheral Interface (SPI) signal into a three-pin signal, wherein the Isolated SPI signal is a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period and an idle period that have a same duration, wherein the three-pin signal includes a first data signal, a second data signal, and a synchronization signal, wherein each of the first format converter and the second format converter is configured to convert the three-pin signal into the Isolated SPI signal.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-16, 22-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the standard SPI signal" in line 6. There is insufficient antecedent basis for this limitation in the claim. It is believed the limitation should instead read --the first standard SPI signal--.
Claim 25 recites the limitation "the standard SPI signal" in line 19. There is insufficient antecedent basis for this limitation in the claim. It is believed the limitation should instead read --the first standard SPI signal--.
All claims that are not specifically addressed are rejected due to a dependency.
Allowable Subject Matter
Claims 12 and 14-32 would be allowable if the Double Patenting and § 112 rejections discussed above were overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 12, the prior art of record does not teach “wherein the first slave BMIC device is configured to: collect measurement data for a plurality of battery cells of the first battery pack; compress the measurement data into fewer data bits using a data compression method based on voltage differences among the plurality of battery cells; pack the compressed measurement data in a data frame; and send the data frame in a burst mode of transmission to the master BMIC device as a first Isolated SPI signal at the first Isolated SPI interface of the first slave BMIC device”, in conjunction with the other limitations in the claim. The closest art of record is Zhu et al. (U.S. Patent Application Publication Number 2022/0305950). Zhu discloses that battery measurement data can be compressed by a controller (see Zhu, paragraph 0037). However, Zhu fails to teach that this compression occurs based on voltage differences among the plurality of battery cells. Zhu further fails to teach that the compressed data is sent in a data frame in a burst mode of transmission to the master BMIC device as a first Isolated SPI signal at the first Isolated SPI interface of the first slave BMIC device. Accordingly, the claim is allowable.
Regarding Claim 17, the prior art of record does not teach “wherein the first interface circuit comprises a first decoding circuit and a first format converter; wherein the second interface circuit comprises a second decoding circuit and a second format converter; a first data bus coupled between outputs of the first decoding circuit and inputs of the second format converter; a second data bus coupled between outputs of the second decoding circuit and inputs of the first format converter; a digital control circuit coupled to the first data bus and the second data bus; and analog-to-digital converters (ADCs) coupled between the digital control circuit and the battery pack; wherein each of the first decoding circuit and the second decoding circuit is configured to decode an Isolated Serial Peripheral Interface (SPI) signal into a three-pin signal, wherein the Isolated SPI signal is a differential signal comprising a positive signal and a complementary negative signal, wherein a bit frame of the positive signal includes a bit period and an idle period that have a same duration, wherein the three-pin signal includes a first data signal, a second data signal, and a synchronization signal, wherein each of the first format converter and the second format converter is configured to convert the three-pin signal into the Isolated SPI signal”, in conjunction with the other limitations in the claim. The closest art of record is Heiling et al. (U.S. Patent Application Publication Number 2019/0097837). Heiling discloses the claimed interfaces and that the SPI protocol may be used to communicate between the interfaces. Heiling further discloses wherein a level shifter may be used for communications between individual interfaces. However, Heiling fails to teach decoding the Isolated SPI signal into a three-pin signal, wherein the three pin signal includes multiple data signals as well as a synchronization signal and further converting the three-pin signal into an Isolated SPI signal as claimed. Accordingly, the claim is allowable.
Regarding Claim 25, the prior art of record does not teach “wherein the battery management system is configured to: send, by the controller, a first standard SPI signal to the master BMIC device, the first standard SPI signal comprising a message that includes a request for battery measurement and an identification (ID) number; convert, by the master BMIC device, the standard SPI signal into a first Isolated SPI signal at the Isolated SPI interface of the master BMIC device; receive, by the first slave BMIC device, the first Isolated SPI signal through the first Isolated SPI interface of the first slave BMIC device; decode, by the first slave BMIC device, the first Isolated SPI signal into digital bits; and process, by the first slave BMIC device, the digital bits”, in conjunction with the other limitations in the claim. The closest art of record is Murnane (U.S. Patent Application Publication Number 2021/0376626). Murnane teaches wherein a plurality of slave BMIC devices receive requests to provide battery measurements from a master BMIC. However, these requests are not received by a controller and are not sent using standard SPI. Rather, the requests are sent using Isolated SPI. Murnane further teaches converting between standard SPI and Isolated SPI, but does not teach any encoding or decoding of those signals. Finally, Murnane does not teach including an identification number within the request. Accordingly, the claim is allowable.
All claims that are not specifically addressed are allowable due to a dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses methods for communicating using the SPI protocol amongst interfaces of a battery management system.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175