DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yanagi (20100270616) in view of Shinohara (20190378925)
Regarding Claim 1, in Figs. 4-13, Yanagi discloses a method for manufacturing a semiconductor device, forming a trench TRA in a semiconductor layer EP (Figs 9 and 10), the trench TRA including a proximate sidewall SS, a distal sidewall TR opposite to the proximate sidewall, and a trench bottom BT interconnecting the proximate and distal sidewalls, the semiconductor layer having an upper surface which is located outside of the trench, and which includes a first surface portion CP1A connected to the distal sidewall, and a second surface portion CP2A connected to the proximate sidewall; forming a mask layer HM/PR2 to cover the trench bottom (Figs 10 and 11), the distal sidewall and the first surface portion of the semiconductor layer so that the proximate sidewall and the second surface portion of the semiconductor layer are exposed from the mask layer; after forming the mask layer, further widening the trench by etching the proximate sidewall and the second surface portion of the semiconductor layer through the mask layer (see Figs. 45-48); forming a dielectric film BI in the widened trench such that the dielectric film includes a proximate end portion located on the etched proximate sidewall, and a distal end portion located on the distal sidewall (see Figs. 11 and 12); forming a drift region DRI in the semiconductor layer such that the dielectric film is located in the drift region; forming a well region WL in the semiconductor layer; forming a source area SO in the semiconductor layer such that the well region is disposed to separate the source area from the drift region; and forming a drain area DR in the drift region such that the dielectric film is located between the source area and the drain area. Yanagi fails to disclose the limitation where an included angle between the etched proximate sidewall and the trench bottom is larger than an included angle between the distal sidewall and the trench bottom. However, Shinohara discloses a semiconductor device where in paragraphs 0008, 0038, 0100 and 0116, the required angle is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required angle in Yanagi as disclosed by Shinohara in order to alleviate the hot carrier effect at the corner portions (see paragraphs 0008, 0032, 0046, 0060, 0071, 0077 and 0110 of Shinohara)
Regarding Claim 2, in Figs. 10-13 of Yanagi, removing the mask layer HM/PR2
after further widening the trench.
Regarding Claim 3, in Figs. 45-50 of Yanagi with angles Theta 1 and Theta 2, each of the proximate end portion and the distal end portion includes a top surface, a bottom surface, and a slanted surface which interconnects the top surface and the bottom surface, the proximate end portion having a first included angle between the top surface and the slanted surface thereof, the distal end portion having a second included angle between the top surface and the slanted surface thereof, the first included angle being smaller than the second included angle, the second included angle ranging from 70 degrees to 90 degrees
Regarding Claim 4, in Figs. 45-50 of Yanagi with angles Theta 1 and Theta 2, the first included angle is in a range of one-third to four-fifth of the second included angle.
Regarding Claim 5, in Figs. 4-13, Yanagi discloses a method for manufacturing a semiconductor device comprising: forming a trench TRA in a semiconductor layer EP (Figs. 9 and 10); forming a dielectric film BI in the trench; forming a drift region DRI in the semiconductor layer such that the dielectric film is located in the drift region; forming a source area SO in the semiconductor layer such that the drift region and the source area are spaced from each other; forming a well region WL in the semiconductor layer, the well region being located between the drift region and the source area; and forming a drain area DR in the drift region, the dielectric film being located between the source area and the drain area, and including a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, wherein formation of the trench TRA includes: patterning the semiconductor layer to form a preliminary trench which includes a proximate sidewall SS, a distal sidewall TR opposite to the proximate sidewall, and a trench bottom BT interconnecting the proximate sidewall and the distal sidewall, the semiconductor layer having a surface portion which is located outside of the preliminary trench, and which is connected to the proximate sidewall; forming a mask layer HM/PR2 to cover the trench bottom and the distal sidewall so that the proximate sidewall and the surface portion of the semiconductor layer are exposed from the mask layer; after forming the mask layer, further widening the preliminary trench by etching the proximate sidewall and the surface portion of the semiconductor layer through the mask layer so as to obtain the trench; and removing the mask layer after further widening the preliminary trench (Figs. 10-13, HM/PR2). Yanagi fails to disclose the asymmetrical relationship. However, Shinohara discloses a semiconductor device where in paragraphs 0008, 0032, 0038, 0046, 0060, 0070, 0071, 0076, 0077, 0080, 0082, 0100, 0110 and 0116, the required asymmetrical relationship (as a result of the angles) are disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required asymmetrical relationship in Yanagi as disclosed by Shinohara in order to alleviate the hot carrier effect at the corner portions (see paragraphs 0008, 0032, 0038, 0046, 0060, 0070, 0071, 0076, 0077, 0080, 0082 and 0110 of Shinohara where the asymmetrical relationship is as a result of the angles associated with bottom left and bottom right corner portions )
Regarding Claim 6, in Yanagi, the dielectric film BI further has a main portion such that the proximate end portion and the distal end portion are spaced apart from each other by the main portion in a first direction, the main portion has a thickness in a second direction transverse to the first direction, and the proximate end portion and the distal end portion have different outer profiles.
Regarding Claim 7, in Yanagi, in paragraph 0085, the thickness of the main portion ranges from 600 Å to 5000 Å.
Regarding Claim 8, in Figs. 45-50 with angles Theta 1 and Theta 2 of Yanagi, each of the proximate end portion and the distal end portion includes a top surface, a bottom surface, and a slanted surface which interconnects the top surface and the bottom surface, the proximate end portion having a first included angle between the top surface and the slanted surface thereof, the distal end portion having a second included angle between the top surface and the slanted surface thereof, the first included angle being smaller than the second included angle.
Regarding Claim 9, in Figs. 45-50, with angles Theta 1 and Theta 2 of Yanagi, the second included angle ranges from 70 degrees to 90 degrees.
Regarding Claim 10, in Figs. 45-50, with angles Theta 1 and Theta 2 of Yanagi, the first included angle is in a range of one-third to four-fifth of the second included angle.
Regarding Claim 11, in Figs 10-13 of Yanagi, forming a gate structure to cover the well region and the proximate end portion of the dielectric film.
Regarding Claim 12, in Figs 10-13 of Yanagi, the gate structure includes a gate electrode and a gate dielectric located beneath the gate electrode.
Regarding Claim 13, in Figs. 45-50 with angles Theta 1 and Theta 2 of Yanagi, each of the first included angle and the second included angle is an acute angle.
Regarding Claim 14, in Figs. 4-13, Yanagi discloses a method for manufacturing a semiconductor device, comprising: forming a trench TRA in a semiconductor layer EP, the trench including a proximate sidewall SS, a distal sidewall TR opposite to the proximate sidewall, and a trench bottom BT interconnecting the proximate and distal sidewalls; forming a mask layer HM/PR2 to cover the trench bottom and the distal sidewall, leaving the proximate sidewall and a surface portion of the semiconductor layer being exposed from the mask layer, the surface portion of the semiconductor layer being located outside of the trench and being connected to the proximate sidewall; after forming the mask layer, further widening the trench by etching the proximate sidewall and the surface portion of the semiconductor layer through the mask layer HM/PR2 (Figs 10-13); forming a dielectric film BI in the widened trench such that the dielectric film includes a proximate end portion located on the etched proximate sidewall, and a distal end portion located on the distal sidewall; forming a drift region DRI in the semiconductor layer such that the dielectric film is located in the drift region; forming a well region WL in the semiconductor layer; forming a source area SO in the semiconductor layer such that the well region is disposed to separate the source area from the drift region; and forming a drain area DR in the drift region such that the dielectric film BI is located between the source area SO and the drain area DR. Yanagi fails to disclose the limitation where least half of volume of the trench is filled by the mask layer. However, in Figs. 8A-8C element 412 or Figs10A-10C, elements 512/59, and in paragraphs 0096-0099, 0101, 0103 and 0106, the required mask layer is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required mask layer relationship in Yanagi as disclosed by Shinohara in order to alleviate the hot carrier effect at the corner portions (see paragraphs 0103 and 0122)
Regarding Claim 15, in Yanagi, the dielectric film BI further has a main portion such that the proximate end portion SS and the distal end portion TR are spaced apart from each other by the main portion in a first direction, the main portion has a thickness in a second direction transverse to the first direction, and the proximate end portion and the distal end portion have different outer profiles (Figs. 10-13 and 45-50).
Regarding Claim 16, in paragraph 0085 of Yanagi, the thickness of the main portion ranges from 600 Å to 5000 Å.
Regarding Claim 17, in Yanagi, each of the proximate end portion SS and the distal end portion TR includes a top surface, a bottom surface, and a slanted surface which interconnects the top surface and the bottom surface; the top surface and the slanted surface of the proximate end portion defines therebetween a first included angle; the top surface and the slanted surface of the distal end portion defines therebetween a second included angle; and the first included angle is smaller than the second included angle (see Figs. 45-50 and angles Theta 1 and Theta 2)
Regarding Claim 18, in Figs. 45-50 with angles Theta 1 and Theta 2 of Yanagi, the first included angle is in a range of one-third to four-fifth of the second included angle.
Regarding Claim 19, in Figs. 10-13 of Yanagi, forming a gate structure to cover the well region and the proximate end portion of the dielectric film.
Regarding Claim 20, in Figs. 10-13 of Yanagi, the gate structure includes a gate electrode and a gate dielectric located beneath the gate electrode.
Relevant Cited Prior Art
Examiner is including Ring 20110248341 as pertinent prior art that is not used in this rejection but that discloses asymmetric STI structure for hot carrier effect suppression. Examiner is also including Huang et al. CN 111463166 as a pertinent prior art that discloses trench isolation structure geometry to counter hot carrier effect. Finally, examiner also including Chuang et al. (20200258987) (Fig. 1C, paragraphs 0026 and 00278) that discloses patterned/shaped STI structure to counter electric field concentration/hot carrier effect.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 12/20/2025