Prosecution Insights
Last updated: October 01, 2026
Application No. 18/757,105

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
Jun 27, 2024
Priority
Jan 12, 2024 — TW 113101411
Examiner
STARK, JARRETT J
Art Unit
Tech Center
Assignee
Siliconware Precision Industries Co., Ltd.
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
913 granted / 1295 resolved
+10.5% vs TC avg
Moderate +12% lift
Without
With
+11.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
65 currently pending
Career history
1351
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
63.3%
+23.3% vs TC avg
§102
16.3%
-23.7% vs TC avg
§112
8.7%
-31.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1295 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group 1 claims 1-9 in the reply filed on 8/10/2026 is acknowledged. Prior Art of Record The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hochberg et al. (US 20160116688 A1). PNG media_image1.png 688 428 media_image1.png Greyscale PNG media_image2.png 644 368 media_image2.png Greyscale PNG media_image3.png 652 438 media_image3.png Greyscale CLAIM 1. Hochberg teaches a electronic package (Hochberg Figs. 1-5), comprising: a carrier structure 160/560 (Hochberg ¶[0038], ¶[0046]); an electronic element 102 disposed on the carrier structure 160/560 and electrically connected to the carrier structure 160/560 (¶[0036], [0038]); a supporting structure 120 “disposed on the carrier structure 160/560 (¶[0038], [0040] Fig. 1A); a semiconductor element 104 disposed on the carrier structure 160/560 and electrically connected to the carrier structure 160/560 (¶[0037], [0038] & Fig. 1A-B); an optoelectronic element 108/109 disposed on the semiconductor element 104 (Fig. 4), electrically connected to the semiconductor element 104, and partially supported by the supporting structure 120 (¶[0039], [0040] & Figs. 1-5). CLAIM 2 Hochberg teaches the electronic package of claim 1, wherein the semiconductor element 104 is an electronic integrated circuit. (¶[0037], [0038] & Fig. 1-5). CLAIM 3 Hochberg teaches the electronic package of claim 1, wherein the optoelectronic element 109 is a photonic integrated circuit. (¶[0039] & Fig. 1-5). CLAIM 4 Hochberg teaches the electronic package of claim 1, wherein the optoelectronic element 108/109 is connected to an optical fiber 131/132/206. (¶[0036], [0039], [0041] & Fig. 1-5) CLAIM 5 Hochberg teaches the electronic package of claim 4, wherein the optical fiber 131/132/206 is passed through at least part of a top of the supporting structure 120. (¶[0040], [0041] & Fig. 1-5). CLAIM 6 Hochberg teaches the electronic package of claim 5, wherein the supporting structure 120 is formed with grooves 151/152/250/256, for at least a part of the optical fiber 131/132/206 to be accommodated in the grooves 151/152/250/256 (¶[0040], [0041] & Fig. 1-5). CLAIM 7. Hochberg teaches the electronic package of claim 5, wherein the supporting structure 120 is provided with a protecting layer 204, for at least a part of the optical fiber 131/132/206 to be fixed by the protecting layer 140 (¶[0040], [0041] & Fig. 1-5). CLAIM 8. Hochberg teaches the electronic package of claim 1, wherein the supporting structure 120 is made of thermal conductive material (¶[0040] & Fig. 1-5). CLAIM 9. Hochberg teaches the electronic package of claim 1, wherein the electronic element 102 is a switch chip. (¶[0036] & Fig. 1-5). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JARRETT J. STARK Primary Examiner Art Unit 2822 9/4/2026 /JARRETT J STARK/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jun 27, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
82%
With Interview (+11.5%)
2y 8m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1295 resolved cases by this examiner. Grant probability derived from career allowance rate.

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