Prosecution Insights
Last updated: July 17, 2026
Application No. 18/757,525

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §101§102§DP
Filed
Jun 28, 2024
Priority
Jun 21, 2019 — TW 108121622 +3 more
Examiner
LEE, CHEUNG
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1062 granted / 1153 resolved
+32.1% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
23 currently pending
Career history
1164
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
60.1%
+20.1% vs TC avg
§102
18.0%
-22.0% vs TC avg
§112
4.2%
-35.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1153 resolved cases

Office Action

§101 §102 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP § 606.01). This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc. The following title is suggested: “SEMICONDUCTOR DEVICE INCLUDING METAL INTERCONNECTIONS HAVING SIDEWALL SPACERS THEREON, AND METHOD FOR FABRICATING THE SAME.” If Applicant does not agree with the suggested title above, Applicant must provide a new title that clearly reflects the invention to which the claims are directed. Claim Objections Claims 1-6 are objected to because of the following informalities: In claim 1, line 6, substitute “comprise” with --comprises-- before “an inclined sidewall.” Claims 2-6 depend from claim 1, so they are objected for the same reason. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. (US Pub. 2013/0001796; hereinafter “Song”). Regarding Claim 1, Song discloses a method for fabricating semiconductor device, comprising: forming a first inter-metal dielectric (IMD) layer 40 (page 6, paragraph 105) on a substrate 10 (see fig. 5A); forming a first metal interconnection (84, 88) (page 7, paragraph 126) in the first IMD layer 40 (see fig. 5J); removing part of the first IMD layer 40 (page 6, paragraph 116; see fig. 5G); forming a spacer (94, 98) (page 7, paragraph 120) adjacent to the first metal interconnection (84, 88) (see figs. 5I and 5J), wherein an inner sidewall of the spacer (94, 98) comprise an inclined sidewall (see fig. 5J); forming a second IMD layer 100 (page 7,paragraph 133) on the spacer (94, 98) and the first metal interconnection (84, 88) and directly contacting the first IMD layer 40 (page 7, paragraph 133; see fig. 5M); and forming a second metal interconnection (153, 156, 159) (page 8, paragraph 150) in the second IMD layer 100 (see fig. 5T) and on the spacer (94, 98) and the first metal interconnection (84, 88) (a middle second metal interconnection 156 is formed on the spacers 94, 98, and left and right second metal interconnections 153, 159 are formed on the first metal interconnections 84, 88; see fig. 5T), wherein a sidewall of the second metal interconnection 156 is aligned with a sidewall of the spacer (94, 98) (the middle second metal interconnection 156 is aligned with outer sidewalls of the spacers 94, 98; see fig. 5T). Regarding Claim 6, Song discloses wherein the second metal interconnection (153, 156, 159) contacts the spacer (94, 98) and the first metal interconnection (84, 88) directly (see fig. 5T). Allowable Subject Matter Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 2 recites the step of forming the second IMD layer comprises: forming a first dielectric layer on the first IMD layer; forming a second dielectric layer on the first dielectric layer; and forming a third dielectric layer on the second dielectric layer. These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record. Claims 3-5 depend from claim 2, so they are objected for the same reason. Double Patenting A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. Claim 1 is rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1 and 7 of prior U.S. Patent No. 12,057,346. This is a statutory double patenting rejection. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 11,791,203 (hereinafter “Pat-203”) in view of Song. Regarding Claim 1, Pat-203 discloses a method for fabricating semiconductor device, comprising: forming a first inter-metal dielectric (IMD) layer on a substrate (see claim 1); forming a first metal interconnection in the first IMD layer (see claim 1); removing part of the first IMD layer (see claim 1); forming a spacer adjacent to the first metal interconnection (see claim 1); forming a second IMD layer on the spacer and the first metal interconnection and directly contacting the first IMD layer (see claim 1); and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection (see claim 1), wherein a sidewall of the second metal interconnection is aligned with a sidewall of the spacer (see claim 7). Pat-203 fails to disclose explicitly wherein an inner sidewall of the spacer comprise an inclined sidewall. However, Song discloses forming spacers (94, 98) (page 7, paragraph 120) having inclined inner sidewalls (see fig. 5T). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a spacer adjacent to a metal interconnection with an inclined inner sidewall, as taught by Song, in order to facilitate conformal formation of the spacer along the metal interconnection, thereby improving process reliability and ensuring adequate insulation between adjacent conductive structures. Regarding Claim 2, Pat-203 discloses wherein the step of forming the second IMD layer comprises: forming a first dielectric layer on the first IMD layer (see claim 2); forming a second dielectric layer on the first dielectric layer (see claim 2); and forming a third dielectric layer on the second dielectric layer (see claim 2). Regarding Claim 3, Pat-203 discloses wherein the first dielectric layer comprises silicon nitride (SiN) (see claim 3). Regarding Claim 4, Pat-203 discloses wherein the second dielectric layer comprises silicon oxide (see claim 4). Regarding Claim 5, Pat-203 discloses wherein the third dielectric layer comprises a low-k dielectric layer (see claim 5). Regarding Claim 6, Pat-203 discloses wherein the second metal interconnection contacts the spacer and the first metal interconnection directly (see claim 6). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHEUNG LEE/Primary Examiner, Art Unit 2812 June 20, 2026
Read full office action

Prosecution Timeline

Jun 28, 2024
Application Filed
Jun 24, 2026
Non-Final Rejection mailed — §101, §102, §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684971
DISPLAY PANEL AND DISPLAY DEVICE
2y 11m to grant Granted Jul 14, 2026
Patent 12685042
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
3y 1m to grant Granted Jul 14, 2026
Patent 12684797
ISOLATION STRUCTURES FOR TRANSISTORS
2y 3m to grant Granted Jul 14, 2026
Patent 12677675
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
2y 10m to grant Granted Jul 07, 2026
Patent 12677425
3D Stackable Memory and Methods of Manufacture
2y 2m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
96%
With Interview (+4.3%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1153 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month