Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. 20160093572 to Chen.
Regarding Claim 15, Chen teaches in Figs. 6-8 at least, a structure, comprising:
a circuit substrate 702;
an integrated chip structure 600 electrically connected to the circuit substrate through a plurality of conductive balls 704, wherein the integrated chip structure comprises:
a first substrate 402;
a first interconnection layer 102 disposed on the first substrate;
a plurality of first conductive pads (706 center) disposed in a center region on the first interconnection layer and electrically connected to a top metallization layer of the first interconnection layer;
a plurality of first conductive posts 304 disposed in a peripheral region on the first interconnection layer and electrically connected to the top metallization layer of the first interconnection layer; and
a second substrate 802 and a second interconnection layer 808 disposed on and overlapped with the plurality of first conductive pads in the center region (see Fig. 8);
a redistribution layer 810 electrically connecting the first interconnection layer and the second interconnection layer of the integrated chip structure to the circuit substrate.
Regarding Claim 18, Chen teaches the structure according to claim 15, further comprising a circuit element 806 disposed in between the integrated chip structure and the circuit substrate, wherein the circuit element is electrically connecting the plurality of conductive balls to the circuit substrate.
Regarding Claim 20, Chen teaches the structure according to claim 15, wherein the integrated chip structure further comprises a dielectric layer 814 and a protection layer sandwiched in between the first interconnection layer and the second substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of U.S. Pat. Pub. No. 20150145142 to Lin et al. (Lin).
Regarding Claim 16, Chen teaches the structure according to claim 15, but does not teach a gap fill layer laterally surrounding the second substrate and the second interconnection layer, wherein sidewalls of the gap fill layer are aligned with sidewalls of the redistribution layer and sidewalls of the first interconnection layer.
However, in analogous art, Lin teaches such a gap fill 258. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Lin to encapsulate and protect the IC and bondwires.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of U.S. Pat. No. 7550833 to Mihara.
Regarding Claim 17, Chen teaches the structure according to claim 16, but does not explicitly teach a plurality of first conductive vias embedded in the gap fill layer and electrically connecting the plurality of first conductive posts to the redistribution layer.
However, in analogous art, Mihara teaches such a structure in Fig. 1 to replace the second substrate and IC of Chen. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Mihara to increase integration density, a constant driving force in semiconductor processing.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding Claim 18, Chen teaches the structure according to claim 16, but does not explicitly teach that a lateral dimension of the circuit element is greater than a lateral dimension of the integrated chip structure. However, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)).
Allowable Subject Matter
Claims 1-14 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 1, the cited prior art does not teach that a width of the first interconnection layer is smaller than a width of the redistribution layer, and a width of the second interconnection layer is equal to a width of the redistribution layer in context with the rest of the claim.
Regarding Claim 8, Marimuthu teaches in Fig. 3g at least, a structure, comprising:
an interposer 142 structure comprising a plurality of bonding pads 144;
an integrated chip structure 124-130 disposed on and electrically connected to the interposer structure, and comprising:
a first chip 102; and
a plurality of conductive balls 140 electrically connecting the integrated chip structure to the plurality of bonding pads of the interposer structure, wherein the plurality of conductive balls is overlapped with and electrically connected to the first chip and the second chip.
Marimuthu does not explicitly teach the first chip comprising a plurality of conductive posts, an etch stop layer disposed over the plurality of conductive posts, and a plurality of first conductive vias electrically connected to the plurality of conductive posts and partially surrounded by the etch stop layer; a second chip embedded in the first chip, wherein the second chip comprises a second substrate, a second interconnection layer and a plurality of second conductive vias electrically connected to the second interconnection layer, and
However, in analogous art, U.S. Pat. No. 7550833 to Mihara teaches such an arrangement in Fig. 1 that may readily replace the single chip of Marimuthu for the purposes of increasing integration. However, neither Marimuthu nor Mihara teach that sidewalls of the second chip are covered up by the etch stop layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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