DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially equal” in claims 4 and 13 is a relative term which renders the claims indefinite. The term “substantially equal” is not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Both claims 4 and 13 contain the phrase (emphasis added), “a width that is substantially equal to a width.” The examiner is unable to determine the metes and bounds of claims 4 and 13 since no tolerance is specified as to what the applicant believes to be “substantially equal.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 14, 15, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kiyotoshi (United States Patent Application Publication No. US 2006/0138595 A1, hereinafter “Kiyotoshi”).
In reference to claim 1, Kiyotoshi discloses a structure which meets the claim. Fig. 1-9 of Kiyotoshi discloses a semiconductor structure which comprises a first electrode (120) over a substrate (101). A first capacitor dielectric layer (122) over an upper surface of the first electrode (120). The upper surface of the first electrode (120) laterally extends to opposing outermost sidewalls of the first capacitor dielectric layer (122). A second electrode (123a) is over the first capacitor dielectric layer (122). The upper surface of the first electrode (120) extends past opposing sides of the second electrode (123a). A second capacitor dielectric layer (124) is over the second electrode (123a). A third electrode (125a) having a lower surface is directly over an upper surface of the second capacitor dielectric layer (124) and is completely confined over the second electrode (123a).
With regard to claim 2, a first metal nitride (121a) is arranged between the first electrode (120) and the first capacitor dielectric layer (122). The first metal nitride (121a) completely covers a lower surface of the first capacitor dielectric layer (122).
In reference to claim 3, the first metal nitride (121a) is titanium nitride (p. 3, paragraph 49) or tantalum nitride (p. 4, paragraph 67).
So far as understood in claim 4, a first metal nitride (121a) has a bottommost surface with a width substantially equal to a width of the first electrode (120).
In reference to claim 5, Kiyotoshi discloses (p. 4, paragraph 67) the use of a composite layered conductive material in the form of TiN/AlCu/TiN for the second electrode (123a). When using the TiN/AlCu/TiN structure for the second electrode (123a), a second metal nitride (TiN) completely covers an upper surface of the middle AlCu electrode layer.
In reference to claim 14, Kiyotoshi discloses a structure which meets the claim. Fig. 1-9 of Kiyotoshi discloses a capacitor structure which comprises a first electrode plate (120, 121a) disposed on a substrate (101). Kiyotoshi discloses (p. 3, paragraph 49) that the first electrode plate (120, 121a) includes a first metal nitride (121a). A first capacitor dielectric layer (122) is disposed on the first electrode plate (120, 121a). A second electrode plate (123a) is disposed on the first capacitor dielectric layer (122). A portion of the first electrode plate (120, 121a) extends beyond an end of the second electrode plate (123a) to form a step. Kiyotoshi discloses (p. 3, paragraph 49) that the second electrode plate (123a) includes a second metal nitride. A second capacitor dielectric layer (124) is disposed on the second electrode plate (123a). A third electrode plate (125a) is disposed on the second capacitor dielectric layer (124). A portion of the second electrode plate (123a) extends beyond an end of the third electrode plate (125a) to form another step. Kiyotoshi discloses (p. 3, paragraph 49) that the third electrode plate (125a) includes a third metal nitride. An inter-metal dielectric layer (128) covers the second electrode plate (123a), the first capacitor dielectric layer (122), and the first electrode plate (120, 121a). A first via (129a – note leftmost vertical portion) penetrates through the inter-metal dielectric layer (128) to contact the first electrode plate (120, 121a) at the portion extending beyond the second electrode plate (123a). A second via (129b) penetrates through the inter-metal dielectric layer (128) to contact the second electrode plate (123a). A third via (129a – note rightmost vertical portion) which penetrates through the inter-metal dielectric layer (128) to contact the third electrode plate (125a).
With regard to claim 15, the first electrode plate (120, 121a) includes a first metal layer (120) and the first metal nitride (121a). Kiyotoshi discloses (p. 4, paragraph 67) the use of a composite layered conductive material in the form of TiN/AlCu/TiN for the electrode material. When using the TiN/AlCu/TiN structure for the second electrode plate (123a), there is a second metal layer (AlCu) and the second metal nitride (TiN) included in the second electrode plate (123a). When using the TiN/AlCu/TiN structure for the third electrode plate (125a), there is a third metal layer (AlCu) and the third metal nitride (TiN) included in the third electrode plate (125a).
In reference to claim 17, Kiyotoshi discloses a method which meets the claim. Fig. 1-9 of Kiyotoshi discloses a method of forming a semiconductor structure which comprises forming a capacitor stack over a substrate (101). The capacitor stack comprises a first electrode layer (120, 121a), a first capacitor dielectric layer (122) over the first electrode layer (120, 121a), a second electrode layer (123, 123a) over the first capacitor dielectric layer (122), a second capacitor dielectric layer (124) over the second electrode layer (123a), and a third electrode layer (125a) over the second capacitor dielectric layer (124). Fig. 2-7 disclose a first patterning process to remove a peripheral part of the third electrode layer (125a), forming a first protective layer (127) over and along sidewalls of the third electrode layer (125a) and also over an upper surface of the second electrode layer (123) after the first patterning process, and removing peripheral parts of the first protective layer (127) and the second electrode layer (123).
With regard to claim 19, fig. 6 and 7 of Kiyotoshi discloses performing a second patterning process to remove the peripheral parts of the first protective layer (127) and the second electrode layer (123). Kiyotoshi discloses (p. 4, paragraph 67) the use of a composite layered conductive material in the form of TiN/AlCu/TiN for the second electrode (123a). When using the TiN/AlCu/TiN structure for the second electrode (123a), a metal nitride (TiN) completely covers an upper surface of the middle AlCu electrode layer such that the metal nitride (TiN) is arranged between the second electrode layer (AlCu) and the second capacitor dielectric layer (124) with the second patterning process removing a peripheral part of the metal nitride (TiN).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kiyotoshi in view of Kim et al. (United States Patent Application Publication No. US 2004/0084709 A1, hereinafter "Kim") and further in view of Jacob et al. (United States Patent Application Publication No. US 2003/0222279 A1, hereinafter "Jacob").
In reference to claim 6, Kiyotoshi does not disclose a first anti-reflection layer that completely covers the second electrode (123a – fig. 1-9) with an upper surface vertically between a top of the second electrode and a top of the third electrode (125a – fig. 1-9) and a second anti-reflection layer disposed vertically above the upper surface of the first anti-reflection layer which completely covers an upper surface of the third electrode (125a – fig. 1-9). However Kim 709 discloses forming an anti-reflection layer over an upper electrode of a capacitor so as to function as an etch stop layer (p. 4, paragraph 42) during the contact formation process shown in figure 8. Jacob discloses that etch stop layers prevent undesired etch damage to upper electrodes of capacitors (p. 4, paragraph 44). In view of Kim 709 and Jacob, it would therefore be obvious to form a first anti-reflection layer to completely cover the second electrode (123a – fig. 1-9 of Kiyotoshi) and a second anti-reflection layer to completely cover the third electrode (125a – fig. 1-9 of Kiyotoshi) in the Kiyotoshi device to prevent any etch damage when forming the contacts to them. In the device of Kiyotoshi constructed in view of Kim 709 and Jacob, the first anti-reflection layer that completely covers the second electrode (123a – fig. 1-9) has an upper surface vertically between a top of the second electrode (123a – fig. 1-9) and a top of the third electrode (125a – fig. 1-9).
In reference to claim 7, Kiyotoshi does not disclose an anti-reflection layer that completely covers the second electrode (123a – fig. 1-9) and has an upper surface vertically between a top of the second electrode (123a – fig. 1-9) and a top of the third electrode (125a – fig. 1-9). However Kim 709 discloses forming an anti-reflection layer over an upper electrode of a capacitor so as to function as an etch stop layer (p. 4, paragraph 42) during the contact formation process shown in figure 8. Jacob discloses that etch stop layers prevent undesired etch damage to upper electrodes of capacitors (p. 4, paragraph 44). In view of Kim 709 and Jacob, it would therefore be obvious to form an anti-reflection layer to completely cover the second electrode (123a – fig. 1-9 of Kiyotoshi) in the Kiyotoshi device to prevent any etch damage when forming the contact to it. Fig. 1-9 of Kim discloses a via (129b) which electrically contacts the second electrode (123a). In the device of Kiyotoshi constructed in view of Kim 709 and Jacob, the a via (129b) extends through the upper surface of the anti-reflection layer to electrically contact the second electrode (123a).
Claims 8, 9, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kiyotoshi in view of Kurihara et al. (United States Patent Application Publication No. US 2006/0180938 A1, hereinafter "Kurihara") and further in view of Baniecki et al. (United States Patent Application Publication No. US 2006/0211212 A1, hereinafter "Baniecki").
In reference to claim 8, fig. 1-9 of Kiyotoshi does not disclose a dielectric structure comprising a lower horizontal segment disposed on the second electrode (123a), a vertical segment extending along a sidewall of the third electrode (125a), and an upper horizontal segment disposed over the third electrode (125a) such that the upper horizontal segment is connected to the lower horizontal segment by the vertical segment. However fig. 2 of Kurihara discloses the use of a dielectric protection structure (51) which coats the entire outer surface of a capacitor in order to protect it from harmful moisture (p. 7, paragraph 101). Baniecki discloses that moisture can cause the capacitor dielectric to deteriorate (p. 1, paragraph 13). In view of Kurihara and Baniecki, it would therefore be obvious to implement a dielectric protection structure which coats the entire outer surface of the Kiyotoshi capacitor such that the dielectric protection structure comprises a lower horizontal segment disposed on the second electrode (123a), a vertical segment extending along a sidewall of the third electrode (125a), and an upper horizontal segment disposed over the third electrode (125a) such that the upper horizontal segment is connected to the lower horizontal segment by the vertical segment. Fig. 9 of Kurihara discloses an inter-metal dielectric (128) formed over the capacitor structure. Thus in the device of Kiyotoshi constructed in view of Kurihara and Baniecki, an inter-metal dielectric (128) is disposed over and laterally surrounds the dielectric structure which coats the entire capacitor structure.
With regard to claim 9, Kurihara discloses that the dielectric protection structure is made of silicon oxide or silicon nitride (p. 7, paragraph 101).
In reference to claim 12, Kiyotoshi discloses (p. 4, paragraph 67) the use of a composite layered conductive material in the form of TiN/AlCu/TiN for the electrode material. When using the TiN/AlCu/TiN structure for the third electrode (125a), there is a metal nitride (TiN) over the third electrode conductor, the AlCu layer. Thus in the device of Kiyotoshi constructed in view of Kurihara and Baniecki, the dielectric protection structure extends over and along a sidewall of the nitride containing material of the third electrode (125a).
So far as understood in claim 13, in the device of Kiyotoshi constructed in view of Kurihara and Baniecki, the dielectric protection structure has a width that is substantially equal to a width of the second electrode (123a – fig. 1-9 of Kiyotoshi).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kiyotoshi in view of Kurihara and further in view of Baniecki.
In reference to claim 16, fig. 1-9 of Kiyotoshi does not disclose a dielectric structure which is disposed on the portion of the second electrode plate (123a) which extends beyond the third electrode plate (125a) and on the third electrode plate (125a). However fig. 2 of Kurihara discloses the use of a dielectric protection structure (51) which coats the entire outer surface of a capacitor in order to protect it from harmful moisture (p. 7, paragraph 101). Baniecki discloses that moisture can cause the capacitor dielectric to deteriorate (p. 1, paragraph 13). In view of Kurihara and Baniecki, it would therefore be obvious to implement a dielectric protection structure which coats the entire outer surface of the Kiyotoshi capacitor such that the dielectric protection structure is disposed on the portion of the second electrode plate (123a) which extends beyond the third electrode plate (125a) and on the third electrode plate (125a). In the device of Kiyotoshi constructed in view of Kurihara and Baniecki, the second via (129b) and the third via (129a – note rightmost vertical portion) penetrate through the dielectric protection structure.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kiyotoshi in view of Rattner et al. (United States Patent Application Publication No. US 2003/0207579 A1, hereinafter “Rattner”).
In reference to claim 18, fig. 1-9 of Kiyotoshi does not disclose that the first protective layer (127) is made of silicon oxide, silicon nitride, or silicon oxynitride. Kiyotoshi discloses that the first protective layer (127), made of a photoresist, is used as a mask (p. 3, paragraphs 52-53). Rattner discloses the known use of silicon oxide, silicon nitride, or silicon oxynitride combined with a photoresist as a mask (p. 6, paragraph 69). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use silicon oxide, silicon nitride, or silicon oxynitride combined with a photoresist as the mask or first protective layer (127) in the method of Kiyotoshi.
Allowable Subject Matter
Claims 10, 11, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor structure that comprises first, second, and third capacitor electrodes over a substrate such that the first electrode laterally extends to the outermost sidewalls of an overlying first capacitor dielectric layer, with the second electrode being over the first capacitor dielectric layer with sides that are confined over the first electrode, with the third electrode being over a second capacitor dielectric layer with sides that are confined over the second electrode in combination with the suggested relative positioning between a dielectric structure on the sidewalls of the third electrode and a via which contacts the first electrode as described by the applicant in claim 10. In the examiner’s opinion, it would also not be obvious to implement a method for forming a semiconductor structure that comprises forming a capacitor stack with first, second, and third capacitor electrode layers with intervening capacitor dielectric layers, performing specific patterning and removal processes to remove peripheral portions of a first protective layer and the second and third electrode layers in combination with the dielectric structure described by the applicant in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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