DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2015/0228550).
Regarding claim 18, Yu et al. discloses, as shown in Figures 1A-1B and 14-16, a method of manufacturing an IC device comprising:
providing at least a first wafer (it is inherent that dies 301,303,305 are formed/dice from a same first wafer) and a second wafer (it is inherent that dies 401,403 are formed/dice from a same second wafer), the first wafer including an array of first integrated circuit dies and the second wafer including an array of second integrated circuit dies;
dicing the first and second wafers into a plurality of individual first and second integrated circuit dies (301,303,305,401,403), respectively;
bonding the individual first integrated circuit dies and the individual second integrated circuit dies together, wherein the first integrated circuit dies and the second integrated circuit dies are alternately arranged;
forming an integrated back-end-of-the-Line (BEOL) structure (103) with a first side in direct contact with the first and second integrated circuit dies;
forming a plurality of conductive joints (bumps, no label, between pads 211 and dies) at a second side of the of the BEOL structure; and
connecting the integrated BEOL structure with a substrate via the conductive joints.
Regarding claim 19, Yu et al. discloses the method further comprising reconfiguring the individual first and second integrated circuit dies onto a reconfigured wafer, and the reconfigured wafer comprises at least one of the first integrated circuit dies and one of the second integrated circuit dies. Note Figures 1A-1B and 14.
Regarding claim 20, Yu et al. discloses forming an integrated back-end-of-the-Line (BEOL) structure (103) further comprising: forming a first dielectric layer in direct contact a first BEOL of the first integrated circuit die and a second BEOL of the second integrated circuit die ([0017], layer 103 may be fabricated multiple layers so a lower layer would be the first dielectric layer and a top layer would be a second dielectric layer), wherein the first dielectric layer comprises one or more conductive features (multiple conductive layers, lines, vias, no label, under the pads 211); and then forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises one or more conductive features are aligned and in direct contact with the one or more conductive features of the first dielectric layer. . Note Figures 1A-1B and 14-16
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 8-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2016/0218082) in view of Joshi et al. (PN 7,087,452).
Regarding claim 1, Lee et al. discloses, as shown in Figures 4-5F, a method of manufacturing an integrated circuit (IC) semiconductor package comprising:
providing a first integrated circuit (IC) die (DIE 1, 560A), wherein the first IC die has a first back-end-of-the-line (BEOL) structure;
providing a second IC die (DIE 2, 560B), wherein the second IC die has a second BEOL structure; and
providing an integrated BEOL structure (450,550), wherein a first side of the integrated BEOL structure is in direct contact with the first BEOL structure and the second BEOL structure.
Lee et al. does not disclose providing a first guard ring to encircle conductive features of the first BEOL and providing a second guard ring to encircle conductive features of the second BEOL. However, Joshi et al. discloses a packaged comprising a guard ring structure (106,340,345,350,355), a first guard ring (106,340,345) is disposed to encircle conductive features of the first BEOL (102), and a second guard ring (106, 350,355) is disposed to encircle conductive features of the second BEOL (102). Note Figures 19-31 of Joshi et al. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the package of Lee et al. having a first guard ring to encircle conductive features of the first BEOL and a second guard ring to encircle conductive features of the second BEOL, such as taught by Joshi et al. in order to prevent external contamination encroaching into the circuitry.
Regarding claim 2, Lee et al. and Joshi et al. disclose the integrated BEOL structure comprises a third guard ring (another one of 106,340,345,350,355) [Figures 19-31].
Regarding claim 3, Lee et al. and Joshi et al. disclose the third guard ring is disposed to encircle conductive features of the integrated BEOL structure [Figures 19-31].
Regarding claim 5, Lee et al. and Joshi et al. disclose the first integrated circuit die comprises a system-on-chip (SoC), and the second integrated circuit die comprises a SoC or a random access memory (RAM) [006], [0071], [0073].
Regarding claim 8, Lee et al. and Joshi et al. disclose further comprising: bonding a third integrated circuit die to the first integrated circuit die and the second integrated circuit die [Figures 19-31].
Regarding claim 9, Lee et al. and Joshi et al. disclose the third integrated circuit die is in direct contact with the integrated BEOL structure [Figures 19-31].
Regarding claim 10, Lee et al. and Joshi et al. disclose the method further comprising: providing a substrate (not shown, [0063]) at a second side of the integrated BEOL structure to support the first integrated circuit die and the second integrated circuit die
Regarding claim 11, Lee et al. and Joshi et al. disclose further comprising: connecting the integrated BEOL structure and the substrate by a plurality of conductive joints (580).
Regarding claim 13, Lee et al. and Joshi et al. disclose the first guard ring is arranged to extend along a perimeter of the first integrated circuit die, and the second guard ring is arranged to extend along a perimeter of the second integrated circuit die [Figures 19-31].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2016/0218082) in view of Joshi et al. (PN 7,087,452) and further in view of Yu et al. (US 2015/0228550).
Lee et al. and Joshi et al. disclose the claimed invention including the method as explained in the above rejection. Lee et al. and Joshi et al. do not disclose the first integrated circuit die is formed with a first height, and the second integrated circuit die is formed with a second height different than the first height. However, Yu et al discloses a first integrated circuit die (401,403) is formed with a first height, and a second integrated circuit die (303,305) is formed with a second height different than the first height. Note Figures 14-16 of Yu et al. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the first and second integrated circuit dies of Lee et al. and Joshi et al. having different height from each other, such as taught by Yu et al. in order to integrate a plurality of different dies to perform the desired function.
Allowable Subject Matter
Claims 4, 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 14-17 are allowed.
8. The following is an examiner's statement of reasons for allowance:
Applicant' s claims 4, 6-7, and 14-17 are allowable over the references of record because none of these references disclose or can be combined to yield the claimed method of manufacturing an integrated circuit comprising ta perimeter portion of the third guard ring is aligned with a portion of the first guard ring, as recited in claim 4; none of these references disclose or can be combined to yield the claimed method of manufacturing an integrated circuit comprising bonding two or more integrated circuit dies side by side with each other, each having a first guard ring structure disposed around a perimeter thereof and a dielectric layer stack having one side in direct contact with the two or more integrated circuit dies, wherein the dielectric layer stack comprises a second guard ring structure, a perimeter portion of the second guard ring is arranged to align with a portion of the first guard ring of the two or more integrated circuit dies, and the second guard ring structure comprises a bridge portion in one of the plurality of dielectric layers, in combination with the remaining claimed limitations of claim 14.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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