Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 and 21-25 in the reply filed on 28 September 2026 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 9-12, 14 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,508,615. Although the claims at issue are not identical, they are not patentably distinct from each other because both applications claim the “same invention”. Specifically, at least claim 1 of this application is a generic claim of a patented species claim 1 of U.S. Patent No. 11,508,615. A species (narrow) claim is said to anticipate a generic (broad) claim thus double patenting exists.
Regarding claim 1, all elements of this claim are anticipated by claim 1 of 11,508,615
Regarding claim 2, all elements of this claim are anticipated by claim 1 of 11,508,615
Regarding claim 9, all elements of this claim are anticipated by claim 10 of 11,508,615
Regarding claim 10, all elements of this claim are anticipated by claim 13 of 11,508,615
Regarding claim 11, all elements of this claim are anticipated by claim 13 of 11,508,615
Regarding claim 12, all elements of this claim are anticipated by claim 10 of 11,508,615
Regarding claim 14, all elements of this claim are anticipated by claim 13 of 11,508,615
Regarding claim 15, all elements of this claim are anticipated by claim 16 of 11,508,615.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eto et al. (US Pat. Pub. 2020/0357680) in view of Haneda (US. Pat. Pub. 2021/0118935).
Regarding claim 21, Eto teaches a semiconductor device structure, comprising:
a conductive structure [fig. 1f, 104]
a second dielectric material, wherein the second dielectric material surrounds a first portion the conductive structure [fig. 1f, 102 surrounds a first portion of 104];
a first spacer layer disposed on the second dielectric material, wherein the first spacer layer surrounds a second portion of the conductive structure [fig. 1f, 126 on 102, surrounds a portion of 104 exposed from 102];
a second spacer layer disposed on the first spacer layer, wherein an air gap is formed between the second spacer layer and the first spacer layer [fig. 1f, 128 on 126, air gap 134 is formed between 126 and 128, air gap is adjacent 126 on the left most 104 and adjacent 128 on the 104 to the right of the left most 104]; and
a third dielectric material disposed on the second spacer layer [fig. 1f, 132].
Eto fails to teach a first dielectric material present with the conductive structure over said first dielectric material but does teach components present below and connected to interconnect structures 104.
Haneda teaches a multi layer interconnect structure with an interlayer dielectric layer between the substrate and interconnect/wiring structures above [fig. 1, substrate 100, interlayer dielectric 110 (first dielectric), wiring layers 130 in dielectric 120 (second dielectric)].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Haneda into the method of Eto by forming a first dielectric material with a conductive structure disposed over said first dielectric material. The ordinary artisan would have been motivated to modify Eto in the manner set forth above for at least the purpose of providing a dielectric layer which prevents components formed on/above the dielectric from being influenced by the surface3 shape of the substrate 100.
Regarding claim 22, Eto in view of Haneda discloses the semiconductor device structure of claim 21, wherein the first space layer comprises a first portion interfacing a first portion of the second spacer layer [Eto, fig. 1f, 128 is in direct contact with 126 which would be interpreted as interfacing].
Regarding claim 23, Eto in view of Haneda teaches the semiconductor device structure of claim 22, wherein the first spacer layer comprises a second portion substantially parallel to a second portion of the second spacer layer, and the air gap is located between the second portion of the first spacer layer and the second portion of the second spacer layer [Eto, fig. 1f, a portion of 126 is parallel with a portion of 128 with air gap 134 between them].
Allowable Subject Matter
Claims 3-8, 13, 24 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1, 2, 9-12, 14 and 15 are rejected under double patenting above but are believed to be allowable if the double patenting rejection is overcome.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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/JOHN M PARKER/Primary Examiner, Art Unit 2899
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