DETAILED ACTION
The Amendment filed May 22, 2026 has been entered. Claims 1-20 are pending. Claims 1, 8 and 15 are independent.
Drawings
The drawings are objected to because:
Figures 1-2 should be designated by a legend such as –Prior Art—because only that which is old is illustrated, and these figures are not invented by the applicant. See MPEP 608.02(g).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,095,529. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,095,529
Comment
Claim 1. A method for a write assist cell, the method comprising: connecting a plurality of write assist cells to a plurality of memory cells,
wherein each of the plurality of write assist cells includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and
wherein each of the plurality of write assist cells includes a write assist control cell and at least one write assist driver cell including a fifth transistor and a sixth transistor;
connecting at least one write assist cell of the plurality of write assist cells to respective ones of the plurality of memory cells in a same column;
connecting each of the first transistor and the third transistor to a first bit line through a first access transistor;
connecting each of the second transistor and the fourth transistor to a second bit line through a second access transistor;
connecting the fifth transistor to the first bit line through a third access transistor; and
connecting the sixth transistor to the second bit line through a fourth access transistor.
Claim 1. A memory device comprising:
a memory array comprising:
a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction; and a plurality of write assist cells connected to the plurality of memory cells,
wherein at least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of
memory cells in a same column;
wherein each of the plurality of write assist cells comprises:
a first transistor; a second transistor; a third transistor; and
a fourth transistor; wherein each of the first transistor and the third transistor is connected to a first bit line through a first access transistor; and wherein each of the second transistor and the fourth transistor is connected to a second bit line through a second access transistor, wherein each write assist cell comprises a write assist
control cell and at least one write assist driver cell,
wherein each of the at least one write assist driver cell comprises:
a fifth transistor; and
a sixth transistor; wherein the fifth transistor is connected to the first bit line through a third access transistor; and wherein the sixth transistor is connected to the second bit line through a fourth access transistor.
Note footnote1
Allowable Subject Matter
Claims 1-20 are rejected but would be allowable if overcoming nonstatutory double patenting as indicated above rejection.
Response to Argument
Applicant’s amendments filed 05/22/2026 have been fully considered.
Regarding drawings objection, it appears there was a misunderstanding between the examiner and the applicant regarding US Patent App. No. 18/354,824 drawing objection. If the applicant submits a new filing for App. No. 18/354,824, the issue will be reconsidered. According, the examiner maintains the objection.
The applicant’s arguments with amending the claims in response to the art rejections have been fully considered and are persuasive. As the examiner has withdrawn the grounds for rejection, the application would be allowable if overcoming nonstatutory double patenting rejection as indicated above.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUNG IL CHO/ Primary Examiner, Art Unit 2825
1 Re independent claims 1, 8 and 15, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights