DETAILED ACTION
The action is responsive to the following communications: the Application filed June 28, 2024 and the information disclosure statement (IDS) filed June 28, 2024. This application is a CON of 18/354,824.
Claims 1-20 are pending. Claims 1, 8 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 28, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because:
Figures 1-2 should be designated by a legend such as –Prior Art—because only that which is old is illustrated, and these figures are not invented by the applicant. See MPEP 608.02(g).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,095,529. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,095,529
Comment
Claim 1. A method for a write assist cell, the method comprising: connecting a plurality of write assist cells to a plurality of memory cells,
wherein each of the plurality of write assist cells includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and
wherein each of the plurality of write assist cells includes a write assist control cell and at least one write assist driver cell including a fifth transistor and a sixth transistor;
connecting at least one write assist cell of the plurality of write assist cells to respective ones of the plurality of memory cells in a same column;
connecting each of the first transistor and the third transistor to a first bit line through a first access transistor;
connecting each of the second transistor and the fourth transistor to a second bit line through a second access transistor;
connecting the fifth transistor to the first bit line through a third access transistor; and
connecting the sixth transistor to the second bit line through a fourth access transistor.
Claim 1. A memory device comprising:
a memory array comprising:
a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction; and a plurality of write assist cells connected to the plurality of memory cells,
wherein at least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of
memory cells in a same column;
wherein each of the plurality of write assist cells comprises:
a first transistor; a second transistor; a third transistor; and
a fourth transistor; wherein each of the first transistor and the third transistor is connected to a first bit line through a first access transistor; and wherein each of the second transistor and the fourth transistor is connected to a second bit line through a second access transistor, wherein each write assist cell comprises a write assist
control cell and at least one write assist driver cell,
wherein each of the at least one write assist driver cell comprises:
a fifth transistor; and
a sixth transistor; wherein the fifth transistor is connected to the first bit line through a third access transistor; and wherein the sixth transistor is connected to the second bit line through a fourth access transistor.
Note footnote1
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 rejected under AIA 35 U.S.C. 103 as being unpatentable over Singh et al. (US 2018/0151220) in view of Lin et al. (US 2018/0301185).
Regarding independent claims 1, 8 and 15, Singh et al. teach a method for a write assist cell, the method comprising:
connecting a plurality of write assist cells (see FIG. 3: 102, 2a-2d, and para. 0023: write-assist cells 2a-2d) to a plurality of memory cells,
wherein each of the plurality of write assist cells includes a first transistor (2a, PMOS in left), a second transistor (2a, PMOS in right), a third transistor (2a, NMOS in left), and a fourth transistor (NMOS in right), and
wherein each of the plurality of write assist cells includes a write assist control cell (102, 2a-2d) and at least one write assist driver cell including a fifth transistor and a sixth transistor;
connecting at least one write assist cell of the plurality of write assist cells to respective ones of the plurality of memory cells in a same column (see FIG. 3);
connecting each of the first transistor (FIG. 3: 2a, PMOS in left) and the third transistor (2a, NMOS in left) to a first bit line (18a) through a first access transistor (16a);
connecting each of the second transistor (FIG. 3: 2a, PMOS in right) and the fourth transistor (NMOS in right) to a second bit line (18b) through a second access transistor (16b).
Singh et al. are silent with respect to one write assist driver cell including a fifth transistor and a sixth transistor; connecting the fifth transistor to the first bit line through a third access transistor; and connecting the sixth transistor to the second bit line through a fourth access transistor.
Lin et al. teach the deficiencies in FIG. 2A and accompanying disclosure, e.g.,
one write assist driver cell (206) including a fifth transistor (INV_A, PFET or NFET) and a sixth transistor (INV_B, PFET or NFET);
connecting the fifth transistor (INV_A) to the first bit line (BL, i.e., primary reference Singh’s BL coupled to Write Assist memory cell) through a third access transistor (N11A); and
connecting the sixth transistor (INV_B) to the second bit line (BLB, i.e., primary reference Singh’s BLB) through a fourth access transistor (N12A).
Singh and Lin are analogous art because they both are directed to SRAM memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Singh with the specified features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Lin et al. to the teaching of Singh et al. such that a memory, as taught by Singh et al., utilizes a write assist driver, as taught by Lin et al., for the purpose of driving write assist circuits along with array of main memory cells properly.
Further, regarding method claim(s), where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
Regarding claim 2, Singh et al. and Lin et al., as combined, teach the limitations of claim 1.
Singh et al. further teach the write assist control cell comprises the first transistor, the second transistor, the third transistor, and the fourth transistor (FIG. 3).
Regarding claim 3, Singh et al. and Lin et al., as combined, teach the limitations of claim 1.
Lin et al. further teach each of the at least one write assist driver cell comprises the fifth transistor and the sixth transistor, the method further comprising: connecting the fifth transistor to the first bit line through the third access transistor; and connecting the sixth transistor to the second bit line through the fourth access transistor (FIG. 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Lin et al. for the same purpose of performing proper write operations successively.
Regarding claims 4 and 20, Singh et al. and Lin et al., as combined, teach the limitations of claims 3 and 15, respectively.
Singh et al. further teach a first subset of memory cells of the plurality of memory cells and a first subset of write assist cells of the plurality of write assist cells are located in a same column (FIG. 3).
Regarding claims 5 and 10, Singh et al. and Lin et al., as combined, teach the limitations of claims 1 and 8, respectively.
Singh et al. further teach controlling each of the first transistor and the second transistor based on a voltage level of the second bit line; and controlling each of the third transistor and the fourth transistor based on a voltage of the first bit line (FIG. 3 and accompanying disclosure).
Regarding claim 6, Singh et al. and Lin et al., as combined, teach the limitations of claim 1.
Singh et al. further teach controlling the first transistor (FIG. 3: 2a) based on an enable signal (i.e., gate signal).
Lin et al. further teach the sixth transistor (FIG. 2A: INV_B) based on an enable signal (i.e., gate signal).
Regarding claims 7, 13 and 17, Singh et al. and Lin et al., as combined, teach the limitations of claims 1, 8 and 15, respectively.
Singh et al. further teach controlling the first access transistor and the second access transistor based on an enable signal (FIG. 3, each gate signal).
Regarding claim 9, Singh et al. and Lin et al., as combined, teach the limitations of claim 8.
Singh et al. further teach the memory cell is an SRAM cell (para. 0002: SRAM).
Regarding claim 11 and 19, Singh et al. and Lin et al., as combined, teach the limitations of claims 8 and 15, respectively.
Lin et al. further teach arranging the memory array along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction (FIG. 2A).
Regarding claim 12, Singh et al. and Lin et al., as combined, teach the limitations of claim 8.
Lin et al. further teach controlling the fifth transistor and the sixth transistor based on an enable signal (FIG. 2A, gate node).
Regarding claim 14, Singh et al. and Lin et al., as combined, teach the limitations of claim 8.
Lin et al. further teach controlling the third access transistor based on a voltage level at the fourth terminal; and controlling the fourth access transistor based on a voltage level at the second terminal (FIG. 2A).
Regarding claim 16, Singh et al. and Lin et al., as combined, teach the limitations of claim 15.
Singh et al. further teach a first subset of memory cells of the plurality of memory cells and a first subset of write assist cells of the plurality of write assist cells are located in a same column, the method further comprising: connecting each memory cell in the first subset of memory cells and each write assist cell in the first subset of write assist cells to the first bit line and the second bit line (FIG. 3).
Regarding claim 18, Singh et al. and Lin et al., as combined, teach the limitations of claim 15.
Lin et al. further teach controlling the third access transistor and the fourth access transistor based on an enable signal (FIG. 2A, gate signal).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 8 and 15, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.