DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al (US 7,839,713).
Regarding the independent claims 1, 9 & 17, Yu et al (Fig. 1-2) shows a conventional SRAM memory circuit, which includes at least a plurality of bit lines (see Fig. 1), a plurality of memory cells arranged in columns, etc., and Fig. 2 shows that each memory cell connected to a pair of bit lines BITA & BITB), and a plurality of clamp circuits (260, Fig. 2), wherein Fig. 2 shows that each clamp circuit (260) comprising a first clamp/logic circuit (261) connected to a first bit line (BITA), and a second clamp/logic circuit (265) connected to a second bit line BITB), wherein the first clamp/logic circuit 261 is configured to selectively clamp the first bit line BITA in response to the memory circuit operating in a particular mode, and wherein the second clamp/logic circuit 265 is configured to selectively clamp the second bit line BITB in response to the memory circuit operating in the particular mode.
[AltContent: textbox (First clamp logic 261 for BITA, & second clamp
Logic 265 for BITB for holding the BLs voltage
at constant potential)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (A pair of bit lines =
BITA & BITB)]
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650
944
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Greyscale
Claims 2 & 10, Fig. 2 further shows that during a particular operation mode (read first or write first), a write multiplexer circuit (221) or a read multiplexer circuit (222) operates accordingly, and these R/W MUX outputs are directly coupled to the pair of bit lines (BITA & BITB), and the output of these bit lines are further to be clamped by each respective clamp/logic circuits (261 for BITA & 265 for BITB) as shown above. The purpose of clamping is to hold or fix the voltage of these bit lines at constant level to avoid bit line noises and/or achieve a stable/efficient power consumption as well.
Claim 4, Fig. 2 shows that in addition to the memory circuit operating in the particular mode (R or W), the pair of multiplexers (221 & 222) respectively couples a particular column of memory cells to a corresponding pair of first and second bit lines (BITA & BITB) of the first and second clamp and logic circuits(261 & 265) is selected for a read or a write operation.
Claims 5-7, Fig. 2 shows that each clamp/logic circuit (261 or 265) either clamps its respective bit line (BITA or BITB), in addition to the memory circuit operating in the particular mode, and either first or second bit lines can be used for a write mode. Additionally, Fig. 3 shows that during a particular mode, a Read/Write enable signals (319 & 329) can be used to enable each pair of bit lines to be clamped respectively, and to be used for a Read or write operation if desired.
[AltContent: arrow][AltContent: textbox (Read or write enable control signals for each BL pairs,
Each pair is coupled to each port of a 2-port memory:
RWENA & RWENB, used for either read or write operation)][AltContent: arrow][AltContent: textbox (A pair of bit lines =
BITA & BITNA, or
BITB & BITNB)][AltContent: arrow][AltContent: arrow]
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762
392
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Greyscale
Claim 9 recites the same language as claim 1, which also taught by Yu et al for the similar reasons above. Additionally, it further recite usage of a latch connected to a sense amp for reading and storing the digital values (0 or 10 readout from the bit lines (BITA & BITB). However, Fig. 2 of Yu (see col. 5, lines 45-48) already stated that “the read sense amplifier 230 is a latch-type read sense amplifier”, which suggest that this sense amp also has a connected/internal latch and configured to store its sensed data as well.
Claims 3 & 11, Yu (col. 9, lines 1-6) stated during a write operation, the read-write enable signal RWENA turns off the control transistors 314 & 316 and disables the clamping circuit 310; thus, inherently suggest that the bit line clamp circuit 310 do not respectively clamp the first or second bit lines in response to the memory system operating in a write first mode as claimed.
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164
1168
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Greyscale
Claims 12-15 & 18-20 recite same subject matter as claims 4-7, which are also disclosed by Yu et al, as already fully discussed above.
Claims 8 & 16, Figs. 2-3 above also show Yu shows the two BL ports (A & B), each port can be used for either reading or writing interpedently as conventional knowledge in thus art, and each port can couple to a respective pair of bit lines (BITA & BITNA) or (BITB & BITNB) if desired.
3. Claims 17, 18 & 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Joshi (US 7,420,858).
Regarding claims 17 & 20, Joshi (Fig. 2) shows a memory circuit and method for operating the memory circuit in a particular mode, which includes at least the following steps:
- selecting a column of memory cells (by using a bit select circuit 108 in Fig. 1), connected to a bit line pair to a clamp and logic circuit (using the pair of clamping transistors 128C & 128T in Fig. 2) during a read or a write operation mode; and
- enabling the clamp and logic circuit based on whether the memory circuit is operating in the particular mode, the column of memory cells connected to the bit line of the clamp and logic circuit is selected during the read or write operation, the bit line connected to the clamp and logic circuit is not being used for a write operation, and the column of memory cells connected to the bit line of the clamp and logic circuit is being used for a read operation.
For example, Fig. 2 bellow that during a read operation, the BL clamp transistors 138C & 138T clamp its respective bit line rc or rt (i.e, 128C for rc line and 128T for rt line), and col. 4 (lines 49-65) stated that the clamping transistors 138T & 138C clamping both select BL outputs 128T & 128C high during the read mode following:
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314
1164
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Greyscale
Claims 18 & 20, Fig. 2 (as discussed above) are shown for clamping during a read first mode. It is used for a read operation and not during a write mode operations as claimed.
[AltContent: textbox (A pair of bit lines = 128C (rc) & 128T (rt)
A pair of clamping transistors = 138C & 138T
During a read operation)][AltContent: arrow][AltContent: arrow]
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796
536
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Greyscale
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827