Prosecution Insights
Last updated: October 02, 2026
Application No. 18/758,816

PROCESSING DEVICE

Non-Final OA §102
Filed
Jun 28, 2024
Priority
Nov 20, 2023 — RE 10-2023-0160471
Examiner
ULLAH, ELIAS
Art Unit
Tech Center
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
729 granted / 858 resolved
+25.0% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
27 currently pending
Career history
867
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
35.6%
-4.4% vs TC avg
§102
53.6%
+13.6% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 858 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 5-7, 11-12, 16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi et al. (Takahashi, US 2016/0247690 A1). Regarding claim 1, Takahashi shows a processing device for processing a substrate (W in FIG. 3) comprising: a vacuum chamber ( Vacuum chamber 20 and [0039]) including a processing space ( see FIG. 3) including an inner wall (inner wall of 51) disposed adjacent to the processing space and an outer wall (outer wall of element 51) disposed on and spaced apart from the inner wall; and a plurality of heaters (heater 87) disposed between the inner wall and the outer wall (inner wall and outer wall of element 51). Regarding claim 2, Takahashi shows a processing device for processing a substrate (W in FIG. 3) further comprising: a first remover ( loading unit 2 as shown in FIG. 1) disposed in the processing space of the vacuum chamber (chamber 20), wherein the first remover includes: a mesh network; and an absorbent disposed in the mesh network ([0035]). Regarding claim 5, Takahashi shows a processing device for processing a substrate (W in FIG. 3) further comprising, wherein the processing space is defined by a first side and a second side facing each other in a first direction ( see FIG. 3 i.e. chamber is square shape) , at least one side wall extending between the first side and the second side, and the first remover is disposed on each of the first side and the second side facing each other in the first direction in the vacuum chamber (see FIG. 1 with respect to FIG. 3). Regarding claim 6, Takahashi shows a processing device for processing a substrate (W in FIG. 3) further comprising, wherein the processing space defined by a first side and a second side facing each other in a first direction, a first side wall and a second side wall facing a second direction crossing the first direction, a third side wall and a fourth side wall facing a third direction crossing each of the first direction and the second direction, the plurality of heaters include a first heater and a second heater, the first heater is disposed adjacent to the first side, and the second heater is disposed adjacent to the second side (see FIG. 3 i.e. heater are in all sides of wall). Regarding claim 7, Takahashi shows a processing device for processing a substrate (W in FIG. 3) further comprising, wherein the first heater (heater 87) is configured to apply a first heating amount and the second heater is configured to apply a second heating amount less than the first heating amount ( underlined limitation considered as function of the heater). Regarding claim 11, Takahashi shows a processing device for processing a substrate (W in FIG. 3) comprising: a vacuum chamber (chamber 20) including a processing space defined by a first side and a second side facing each other in a first direction (see FIG. 3), a first side wall and a second side wall facing a second direction crossing the first direction, a third side wall and a fourth side wall facing a third direction crossing each of the first direction and the second direction ( see FIG. 3 i.e. process chamber 20 is square shape), wherein each of the first side wall, the second side wall, the third side wall, and the fourth side wall include an inner wall disposed adjacent to the processing space and an outer wall disposed on and spaced apart from the inner wall; a plurality of heaters (heater 87) disposed between the inner wall and the outer wall; and a stage disposed between the first side and the second side in the processing space (see FIG. 3). Regarding claim 12, Takahashi shows a processing device for processing a substrate (W in FIG. 3) further comprising: a first remover (loader 2) disposed in the processing space of the vacuum chamber, wherein the first remover includes: a mesh network; and an absorbent disposed in the mesh network ( see FIG. 1 with respect to FIG. 3). Regarding claim 16, Takahashi shows a processing device for processing a substrate (W in FIG. 3) further comprising, wherein the plurality of heaters ( heater 87) include a first heater and a second heater, the first heater is disposed adjacent to the first side, the second heater is disposed adjacent to the second side, and the first heater is configured to apply a first heating amount and the second heater is configured to apply a second heating amount different than the first heating amount (see FIG. 3). Regarding claim 19, Takahashi shows a processing device for processing a substrate (W in FIG. 3) comprising: a vacuum chamber (cumber 20) including a processing space defined by a first side and second side facing each other in a first direction (see FIG. 3) and at least one side wall extending between the first side and the second side, the at least one side wall including an inner wall disposed adjacent to the processing space and an outer wall disposed on and spaced apart from the inner wall; and a plurality of heaters (heater 87) disposed between the inner wall and the outer wall and including a first heater disposed adjacent to the first side and a second heater disposed adjacent to the second side (see FIG. 3). Allowable Subject Matter Claims 2-3, 8-10, 13-15, 17-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 28, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751024
HETEROJUNCTION BIPOLAR TRANSISTOR AND BASE-COLLECTOR GRADE LAYER
2y 5m to grant Granted Sep 29, 2026
Patent 12745497
LIGHT EMITTING CHIP AND MANUFACTURING METHOD FOR THE SAME, AND LIGHT EMITTING DEVICE
3y 6m to grant Granted Sep 22, 2026
Patent 12740442
VIA STRUCTURE FOR EMBEDDED COMPONENT AND METHOD FOR MAKING SAME
4y 3m to grant Granted Sep 15, 2026
Patent 12733519
MULTICHIP MODULE THERMAL MANAGEMENT THROUGH BACKSIDE METAL
3y 5m to grant Granted Sep 08, 2026
Patent 12733550
POWER ELECTRONICS ARRANGEMENT WITH PARALLEL CONNECTED SEMICONDUCTOR SWITCHES, POWER ELECTRONICS DEVICE, MOTOR VEHICLE, AND METHOD FOR PRODUCING A POWER ELECTRONICS ARRANGEMENT
3y 3m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+7.8%)
2y 4m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 858 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month