DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/28/2024, 7/7/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1 and 10 are objected to because of the following informalities:
In claim 1, line 11, the limitation of “nanostructures spacing” should be corrected into “nanostructures”. Appropriate correction is required.
In claim 10, line 11, the limitation of “nanostructures spacing” should be corrected into “nanostructures”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 and 10-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 5 and 8-9 of U.S. Patent No. 12,040,191 in view of Hsu (US 2021/0066137).
Regarding claim 1, Pat '191 discloses, in claims 1, 5, and 8, a semiconductor device, comprising:
a first transistor comprising:
a plurality of first nanostructures disposed over a first portion of a substrate, wherein two adjacent nanostructures of the plurality of first nanostructures are separated by a first spacing ("first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure; the first nanostructures have a first vertical spacing", in claim 1 of Pat '191, is interpreted as the same limitation), and
a first gate structure wrapping around each of the plurality of first nano structures ("a first interfacial layer wrapping around each of the first nanostructures; a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures" and “a first work function metal layer over the first high-k dielectric layer and wrapping around each of the first nanostructures; a first bulk metal layer over the first work function metal layer”, in claims 1 and 8 of Pat '191, are interpreted as the same limitation);
a second transistor comprising:
a plurality of second nanostructures disposed over a second portion of the substrate, wherein two adjacent nanostructures of the plurality of second nanostructures spacing are separated by a second spacing greater than the first spacing ("second nanostructures vertically spaced one from another over the substrate in an input/output (I/O) region of the semiconductor structure; the second nanostructures have a second vertical spacing, and the first vertical spacing is smaller than the second vertical spacing by about 4 Å to about 20 Å", in claim 1 of Pat '191, is interpreted as the same limitation), and
a second gate structure wrapping around each of the plurality of second nano structures ("a second interfacial layer wrapping around each of the second nanostructures; a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures" and “a second work function metal layer over the second high-k dielectric layer and wrapping around each of the second nanostructures; a second bulk metal layer over the second work function metal layer”, in claims 1 and 8 of Pat '191, are interpreted as the same limitation);
a first isolation feature laterally adjacent to the first portion of the substrate ("a first isolation feature in the core region of the semiconductor structure and adjacent to a first top portion of the substrate", in claim 5 of Pat '191, is interpreted as the same limitation); and
a second isolation feature laterally adjacent to the second portion of the substrate ("a second isolation feature in the I/O region of the semiconductor structure and adjacent to a second top portion of the substrate", in claim 5 of Pat '191, is interpreted as the same limitation).
Pat '191 does not explicitly disclose a top surface of the first isolation feature is lower than a top surface of the first portion of the substrate; a top surface of the second isolation feature is lower than a top surface of the second portion of the substrate.
Hsu teaches, in at least figures 2-3, 14A-14B, 20A-20B, and related text, the device comprising a top surface of the first isolation feature (206 of 201, [22], figures) is lower than a top surface of the first portion of the substrate (204, [22]); a top surface of the second isolation feature (206 of 202, [22], figures) is lower than a top surface of the second portion of the substrate (204, [22]), for the purpose of providing semiconductor device in the I/O area having a higher threshold voltage without degradation of performance ([12]).
Pat '191 and Hsu are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '191 with the specified features of Hsu because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '191 to have the top surface of the first isolation feature being lower than a top surface of the first portion of the substrate; the top surface of the second isolation feature being lower than a top surface of the second portion of the substrate, as taught by Hsu, for the purpose of providing semiconductor device in the I/O area having a higher threshold voltage without degradation of performance ([12], Hsu).
Regarding claim 2, Pat '191 in view of Hsu discloses the semiconductor device of claim 1 as described above.
Hsu further teaches, in at least figures 2-3, 14A-14B, 20A-20B, and related text, epitaxial source/drain features coupled to the plurality of first nanostructures (210B, [30]) and two opposite ends of the plurality of first nanostructures (210B, [30]) contact the epitaxial source/drain features (214, [25]), for the purpose of providing semiconductor device in the I/O area having a higher threshold voltage without degradation of performance ([12]).
Regarding claim 3, Pat '191 in view of Hsu discloses the semiconductor device of claim 1 as described above.
Pat '191 further discloses, in claims 1 and 8, the first gate structure comprises a first gate dielectric layer and a first conductive layer over the first gate dielectric layer ("a first interfacial layer wrapping around each of the first nanostructures; a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures" and “a first work function metal layer over the first high-k dielectric layer and wrapping around each of the first nanostructures; a first bulk metal layer over the first work function metal layer”, in claims 1 and 8 of Pat '191, are interpreted as the same limitation), the second gate structure comprises a second gate dielectric layer and a second conductive layer over the second gate dielectric layer ("a second interfacial layer wrapping around each of the second nanostructures; a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures" and “a second work function metal layer over the second high-k dielectric layer and wrapping around each of the second nanostructures; a second bulk metal layer over the second work function metal layer”, in claims 1 and 8 of Pat '191, are interpreted as the same limitation).
Pat '191 does not explicitly disclose a thickness of the first gate dielectric layer is different than a thickness of the second gate dielectric layer.
Pat '191 teaches, in claim 9, a thickness of the first gate dielectric layer is different than a thickness of the second gate dielectric layer ("a thickness of the first portion of the first interfacial layer is smaller than a thickness of the first portion of the second interfacial layer by about 2 Å to about 10 Å”, in claim 9 of Pat '191, is interpreted as the same limitation), for the purpose of adjusting the threshold voltage of the gate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '191 to have the thickness of the first gate dielectric layer is different than a thickness of the second gate dielectric layer, as taught by claim 9 of Pat '191, for the purpose of adjusting the threshold voltage of the gate.
Regarding claim 4, Pat '191 in view of Hsu discloses the semiconductor device of claim 3 as described above.
Pat '191 further discloses, in claim 1, the first gate dielectric layer comprises a first interfacial layer and a first high- k dielectric layer on the first interfacial layer ("a first interfacial layer wrapping around each of the first nanostructures; a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures”, in claim 1 of Pat '191, is interpreted as the same limitation), the second gate dielectric layer comprises a second interfacial layer and a second high-k dielectric layer on the second interfacial layer ("a second interfacial layer wrapping around each of the second nanostructures; a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures”, in claim 1 of Pat '191, is interpreted as the same limitation).
Pat '191 further teaches, in claim 9, a thickness of the second interfacial layer is greater than a thickness of the first interfacial layer ("a thickness of the first portion of the first interfacial layer is smaller than a thickness of the first portion of the second interfacial layer by about 2 Å to about 10 Å”, in claim 9 of Pat '191, is interpreted as the same limitation), for the purpose of adjusting the threshold voltage of the gate.
Regarding claim 5, Pat '191 in view of Hsu discloses the semiconductor device of claim 4 as described above.
Pat '191 in view of Hsu does not explicitly disclose a thickness of each of the first and second high-k dielectric layers is in a range between about 1nm and about 2nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of each of the first and second high-k dielectric layers as claimed in claim 5 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of each of the first and second high-k dielectric layers as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- a thickness of each of the first and second high-k dielectric layers is in a range between about 1nm and about 2nm) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Regarding claim 6, Pat '191 in view of Hsu discloses the semiconductor device of claim 1 as described above.
Hsu further teaches, in at least figures 2-3, 14A-14B, 20A-20B, and related text, the top surface of the first isolation feature (206 of 201, [22], figures) is a curved surface, for the purpose of providing semiconductor device in the I/O area having a higher threshold voltage without degradation of performance ([12]).
Regarding claim 7, Pat '191 in view of Hsu discloses the semiconductor device of claim 1 as described above.
Pat '191 further discloses, in claim 1, the plurality of first nanostructures has a first vertical pitch, the plurality of second nanostructures has a second vertical pitch substantially equal to the first vertical pitch ("the first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch, and the first vertical pitch is about same as the second vertical pitch”, in claim 1 of Pat '191, is interpreted as the same limitation).
Regarding claim 10, Pat '191 discloses, in claims 1, 5, and 8, a semiconductor device, comprising:
a plurality of first nanostructures, wherein two adjacent nanostructures of the plurality of first nanostructures are separated by a first spacing ("first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure; the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing, and the first vertical spacing is smaller than the second vertical spacing by about 4 Å to about 20 Å”, in claim 1 of Pat '191, is interpreted as the same limitation);
a first isolation feature ("a first isolation feature in the core region of the semiconductor structure and adjacent to a first top portion of the substrate”, in claim 5 of Pat '191, is interpreted as the same limitation);
a first gate structure having a first portion wrapping around each of the plurality of first nanostructures ("a first interfacial layer wrapping around each of the first nanostructures; a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures" and “a first work function metal layer over the first high-k dielectric layer and wrapping around each of the first nanostructures; a first bulk metal layer over the first work function metal layer”, in claims 1 and 8 of Pat '191, are interpreted as the same limitation);
a plurality of second nanostructures, wherein two adjacent nanostructures of the plurality of second nanostructures spacing are separated by a second spacing greater than the first spacing ("second nanostructures vertically spaced one from another over the substrate in an input/output (I/O) region of the semiconductor structure; the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing, and the first vertical spacing is smaller than the second vertical spacing by about 4 Å to about 20 Å”, in claim 1 of Pat '191, is interpreted as the same limitation);
a second isolation feature ("a second isolation feature in the I/O region of the semiconductor structure and adjacent to a second top portion of the substrate”, in claim 5 of Pat '191, is interpreted as the same limitation);
a second gate structure having a first portion wrapping around each of the plurality of second nanostructures ("a second interfacial layer wrapping around each of the second nanostructures; a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures" and “a second work function metal layer over the second high-k dielectric layer and wrapping around each of the second nanostructures; a second bulk metal layer over the second work function metal layer”, in claims 1 and 8 of Pat '191, are interpreted as the same limitation).
Pat '191 does not explicitly disclose a first protrusion extending from a substrate; a plurality of first nanostructures disposed over the first protrusion; a first isolation feature adjacent to the first protrusion; a first gate structure having a second portion on the first isolation feature, wherein a bottom surface of the second portion of the first gate structure is lower than a top surface of the first protrusion; a second protrusion extending from the substrate; a plurality of second nanostructures disposed over the second protrusion; a second isolation feature adjacent to the second protrusion; a second gate structure having a second portion on the second isolation feature, wherein a bottom surface of the second portion of the second gate structure is lower than a top surface of the second protrusion.
Hsu teaches, in at least figures 2-3, 14A-14B, 20A-20B, and related text, the device comprising a first protrusion (protrusion of 204 in 201, figures) extending from a substrate (204, [22]); a plurality of first nanostructures (210B, [31]) disposed over the first protrusion (protrusion of 204 in 201, figures); a first isolation feature (206 of 201, [22], figures) adjacent to the first protrusion (protrusion of 204 in 201, figures); a first gate structure (242/244/252, [33], [34], [41]) having a second portion on the first isolation feature (206 of 201, [22], figures), wherein a bottom surface of the second portion of the first gate structure (242/244/252, [33], [34], [41]) is lower than a top surface of the first protrusion (protrusion of 204 in 201, figures); a second protrusion (protrusion of 204 in 202, figures) extending from the substrate (204, [22]); a plurality of second nanostructures (210B’, [31]) disposed over the second protrusion (protrusion of 204 in 202, figures); a second isolation feature (206 of 202, [22], figures) adjacent to the second protrusion (protrusion of 204 in 202, figures); a second gate structure (236/250/252, [33], [41]) having a second portion on the second isolation feature (206 of 202, [22], figures), wherein a bottom surface of the second portion of the second gate structure (236/250/252, [33], [41]) is lower than a top surface of the second protrusion (protrusion of 204 in 202, figures), for the purpose of providing semiconductor device in the I/O area having a higher threshold voltage without degradation of performance ([12]).
Pat '191 and Hsu are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '191 with the specified features of Hsu because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '191 to have the first protrusion extending from a substrate; the plurality of first nanostructures disposed over the first protrusion; the first isolation feature adjacent to the first protrusion; the first gate structure having a second portion on the first isolation feature, wherein a bottom surface of the second portion of the first gate structure is lower than a top surface of the first protrusion; the second protrusion extending from the substrate; the plurality of second nanostructures disposed over the second protrusion; the second isolation feature adjacent to the second protrusion; the second gate structure having a second portion on the second isolation feature, wherein a bottom surface of the second portion of the second gate structure is lower than a top surface of the second protrusion, as taught by Hsu, for the purpose of providing semiconductor device in the I/O area having a higher threshold voltage without degradation of performance ([12], Hsu).
Regarding claim 11, Pat '191 in view of Hsu discloses the semiconductor device of claim 10 as described above.
Pat '191 further discloses, in claims 1 and 8, the first gate structure comprises a first interfacial layer having a first thickness and a first high-k dielectric layer on the first interfacial layer and having a second thickness, wherein the second gate structure comprises a second interfacial layer having a third thickness and a second high- k dielectric layer on the second interfacial layer and having the second thickness ("a first interfacial layer wrapping around each of the first nanostructures; a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures; a second interfacial layer wrapping around each of the second nanostructures; a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures " and “a first work function metal layer over the first high-k dielectric layer and wrapping around each of the first nanostructures; a first bulk metal layer over the first work function metal layer; a second work function metal layer over the second high-k dielectric layer and wrapping around each of the second nanostructures; a second bulk metal layer over the second work function metal layer”, in claims 1 and 8 of Pat '191, are interpreted as the same limitation).
Pat '191 does not explicitly disclose a second interfacial layer having a third thickness greater than the first thickness.
Pat '191 teaches, in claim 9, a second interfacial layer having a third thickness greater than the first thickness ("a thickness of the first portion of the first interfacial layer is smaller than a thickness of the first portion of the second interfacial layer by about 2 Å to about 10 Å”, in claim 9 of Pat '191, is interpreted as the same limitation), for the purpose of adjusting the threshold voltage of the gate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '191 to have the second interfacial layer having a third thickness greater than the first thickness, as taught by claim 9 of Pat '191, for the purpose of adjusting the threshold voltage of the gate.
Regarding claim 12, Pat '191 in view of Hsu discloses the semiconductor device of claim 11 as described above.
Pat '191 further teaches, in claim 9, a dimensional difference between the first thickness and the third thickness is in a range between about 2 Å and about 10 Å ("a thickness of the first portion of the first interfacial layer is smaller than a thickness of the first portion of the second interfacial layer by about 2 Å to about 10 Å”, in claim 9 of Pat '191, is interpreted as the same limitation), for the purpose of adjusting the threshold voltage of the gate.
Regarding claim 13, Pat '191 in view of Hsu discloses the semiconductor device of claim 11 as described above.
Pat '191 does not explicitly disclose the second thickness is in a range between about 1nm and about 2nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of each of the first and second high-k dielectric layers as claimed in claim 13 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of each of the first and second high-k dielectric layers as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the second thickness is in a range between about 1nm and about 2nm) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Regarding claim 14, Pat '191 in view of Hsu discloses the semiconductor device of claim 11 as described above.
Pat '191 further discloses, in claims 1 and 2, the plurality of first nanostructures and the plurality of second nanostructures has a same vertical pitch ("the first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch, and the first vertical pitch is about same as the second vertical pitch”, in claim 1 of Pat '191, is interpreted as the same limitation), and a thickness of a bottommost nanostructure of the plurality of second nanostructures is less than a thickness of a bottommost nanostructure of the plurality of first nanostructures ("a thickness of each nanostructure of the first nanostructures is greater than a thickness of each nanostructure of the second nanostructures”, in claim 2 of Pat '191, is interpreted as the same limitation).
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5 and 8 of U.S. Patent No. 12,040,191 in view of Hsu (US 2021/0066137), and further in view of Lan (US 2021/0159311).
Regarding claim 8, Pat '191 in view of Hsu discloses the semiconductor device of claim 7 as described above.
Pat '191 in view of Hsu does not explicitly disclose a thickness of one the plurality of first nanostructures is less than a thickness of one of the plurality of second nanostructures.
Lan teaches, in at least figures 10E-1, 10E-2, 10E-3, and related text, the device comprising a thickness of one the plurality of first nanostructures (108e-3, [103]) is less than a thickness of one of the plurality of second nanostructures (108e-2, [103]), for the purpose of providing semiconductor device including transistors with different designs ([17]) thereby improved performance.
Pat '191, Hsu, and Lan are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '191 in view of Hsu with the specified features of Lan because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '191 in view of Hsu to have the thickness of one the plurality of first nanostructures being less than a thickness of one of the plurality of second nanostructures, as taught by Lan, for the purpose of providing semiconductor device including transistors with different designs ([17], Lan) thereby improved performance.
Claims 9 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5 and 8 of U.S. Patent No. 12,040,191 in view of Hsu (US 2021/0066137), and further in view of Liaw (US 2020/0343387).
Regarding claim 9, Pat '191 in view of Hsu discloses the semiconductor device of claim 7 as described above.
Pat '191 in view of Hsu does not explicitly disclose a width of one the plurality of first nanostructures is less than a width of one of the plurality of second nanostructures.
Liaw teaches, in at least figures 7-8 and related text, the device comprising a width of one the plurality of first nanostructures (122, [27]) is less than a width of one of the plurality of second nanostructures (142, [27]), for the purpose of providing flexible design integration schemes to accommodate different circuits in the same IC ([17]).
Pat '191, Hsu, and Liaw are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '191 in view of Hsu with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '191 in view of Hsu to have the width of one the plurality of first nanostructures being less than a width of one of the plurality of second nanostructures, as taught by Liaw, for the purpose of providing flexible design integration schemes to accommodate different circuits in the same IC ([17], Liaw).
Regarding claim 15, Pat '191 in view of Hsu discloses the semiconductor device of claim 14 as described above.
Pat '191 in view of Hsu does not explicitly disclose a width of the bottommost nanostructure of the plurality of second nanostructures is less than a width of the bottommost nanostructure of the plurality of first nanostructures.
Liaw teaches, in at least figures 7-8 and related text, the device comprising a width of the bottommost nanostructure of the plurality of second nanostructures (122, [27]) is less than a width of the bottommost nanostructure of the plurality of first nanostructures (142, [27]), for the purpose of providing flexible design integration schemes to accommodate different circuits in the same IC ([17]).
Pat '191, Hsu, and Liaw are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '191 in view of Hsu with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '191 in view of Hsu to have the width of the bottommost nanostructure of the plurality of second nanostructures being less than a width of the bottommost nanostructure of the plurality of first nanostructures, as taught by Liaw, for the purpose of providing flexible design integration schemes to accommodate different circuits in the same IC ([17], Liaw).
Claims 16, 18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 9 and 14-15 of U.S. Patent No. 12,040,191 in view of Liaw (US 2020/0343387).
Regarding claim 16, Pat '191 discloses, in claims 9 and 14, a semiconductor device, comprising: a first transistor comprising a plurality of first nanostructures over a substrate; a first structure adjacent to the plurality of first nanostructures; a second transistor comprising a plurality of second nanostructures over the substrate; and a second structure adjacent to the plurality of second nanostructures, wherein a distance between the first structure and one of the plurality of first nanostructures is different than a distance between the second structure and one of the plurality of second nanostructures ("first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure; a first interfacial layer comprising a first portion wrapping around each of the first nanostructures; a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures; second nanostructures vertically spaced one from another over the substrate in an input/output (I/O) region of the semiconductor structure; a second interfacial layer comprising a first portion wrapping around each of the second nanostructures; a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures; a first dielectric fin disposed adjacent to a side of the first nanostructures and laterally spaced from the first nanostructures by a first gap; and a second dielectric fin disposed adjacent to a side of the second nanostructures and laterally spaced from the second nanostructures by a second gap, wherein the second gap is greater than the first gap by about 2 Å to about 10 Å” and “a first work function metal layer over the first high-k dielectric layer and wrapping around each of the first nanostructures; a second work function metal layer over the second high-k dielectric layer and wrapping around each of the second nanostructures; a first bulk metal layer over the first work function metal layer; and a second bulk metal layer over the second work function metal layer”, in claims 9 and 14 of Pat '191, are interpreted as the same limitation).
Pat '191 does not explicitly disclose a top surface of the first structure is above a top surface of a bottommost nanostructure of the plurality of first nanostructures; a top surface of the second structure is above a top surface of a bottommost nanostructure of the plurality of second nanostructures.
Liaw teaches, in at least figure 7 and related text, the device comprising a top surface of the first structure (132 adjacent to 122, [24], figure) is above a top surface of a bottommost nanostructure of the plurality of first nanostructures (122, [27]); a top surface of the second structure (132 adjacent to 142, [24], figure) is above a top surface of a bottommost nanostructure of the plurality of second nanostructures (142, [27]), for the purpose of providing gate end dielectric layer at the boundaries of the cells for isolation purposes ([24]).
Pat '191 and Liaw are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '191 with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '191 to have the top surface of the first structure being above a top surface of a bottommost nanostructure of the plurality of first nanostructures; the top surface of the second structure being above a top surface of a bottommost nanostructure of the plurality of second nanostructures, as taught by Liaw, for the purpose of providing gate end dielectric layer at the boundaries of the cells for isolation purposes ([24], Liaw).
Regarding claim 18, Pat '191 in view of Liaw discloses the semiconductor device of claim 16 as described above.
Pat '191 further discloses, in claim 15, a first dielectric layer; a second dielectric layer extending along sidewall and bottom surface of the first dielectric layer (all limitations are the same with the limitations recited in claim 15 of Pat '191).
Regarding claim 20, Pat '191 in view of Liaw discloses the semiconductor device of claim 16 as described above.
Pat '191 does not explicitly disclose a vertical pitch of the plurality of first nanostructures is substantially equal to a vertical pitch of the plurality of second nanostructures, and a thickness of one of the plurality of first nanostructures is different than a thickness of one of the plurality of second nanostructures.
Pat '191 teaches, in claims 1 and 2, a vertical pitch of the plurality of first nanostructures is substantially equal to a vertical pitch of the plurality of second nanostructures ("the first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch, and the first vertical pitch is about same as the second vertical pitch”, in claim 1 of Pat '191, is interpreted as the same limitation), and a thickness of one of the plurality of first nanostructures is different than a thickness of one of the plurality of second nanostructures ("a thickness of each nanostructure of the first nanostructures is greater than a thickness of each nanostructure of the second nanostructures”, in claim 1 of Pat '191, is interpreted as the same limitation), for the purpose of adjusting the threshold voltage of the gate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 9 of Pat '191 to have the vertical pitch of the plurality of first nanostructures being substantially equal to a vertical pitch of the plurality of second nanostructures, and the thickness of one of the plurality of first nanostructures being different than a thickness of one of the plurality of second nanostructures, as taught by claims 1 and 2 of Pat '191, for the purpose of adjusting the threshold voltage of the gate.
Claims 17 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 14 of U.S. Patent No. 12,040,191 in view of Liaw (US 2020/0343387), and further in view of Lan (US 2021/0159311).
Regarding claim 17, Pat '191 in view of Liaw discloses the semiconductor device of claim 16 as described above.
Pat '191 in view of Liaw does not explicitly disclose the first structure comprises a silicon-containing material.
Lan teaches, in at least figurse 10E-2, 10E-3, and related text, the device comprising the first structure (120/122, [34], [35]) comprises a silicon-containing material, for the purpose of providing semiconductor device including transistors with different designs ([17]) thereby improved performance.
Pat '191, Liaw, and Lan are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '191 in view of Liaw with the specified features of Lan because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '191 in view of Liaw to have the first structure comprising a silicon-containing material, as taught by Lan, for the purpose of providing semiconductor device including transistors with different designs ([17], Lan) thereby improved performance.
Regarding claim 19, Pat '191 in view of Liaw discloses the semiconductor device of claim 16 as described above.
Pat '191 in view of Liaw does not explicitly disclose an isolation feature adjacent to a portion of the substrate disposed under the plurality of first nanostructures, wherein a top surface of the isolation feature is lower than a top surface of the portion of the substrate, and wherein the first structure is disposed over the isolation feature.
Lan teaches, in at least figurse 10E-2, 10E-3, and related text, the device comprising an isolation feature (114, [27]) adjacent to a portion of the substrate (102, [27]) disposed under the plurality of first nanostructures (108e-3, [103]), wherein a top surface of the isolation feature (114, [27]) is lower than a top surface of the portion of the substrate (102, [27]), and wherein the first structure (120/122, [34], [35]) is disposed over the isolation feature (114, [27]), for the purpose of providing semiconductor device including transistors with different designs ([17]) thereby improved performance.
Pat '191, Liaw, and Lan are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '191 in view of Liaw with the specified features of Lan because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '191 in view of Liaw to have the isolation feature adjacent to a portion of the substrate disposed under the plurality of first nanostructures, wherein a top surface of the isolation feature is lower than a top surface of the portion of the substrate, and wherein the first structure is disposed over the isolation feature, as taught by Lan, for the purpose of providing semiconductor device including transistors with different designs ([17], Lan) thereby improved performance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7 and 10-14 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hsu (US 2021/0066137).
Regarding claim 1, Hsu discloses, in at least figures 2-3, 19A-20B, and related text, a semiconductor device, comprising:
a first transistor (201, [15], [16]) comprising:
a plurality of first nanostructures (210B, [31]) disposed over a first portion of a substrate (204, [22]), wherein two adjacent nanostructures of the plurality of first nanostructures (210B, [31]) are separated by a first spacing (S1, [31]), and
a first gate structure (242/244/252, [33], [34], [41]) wrapping around each of the plurality of first nano structures (210B, [31]);
a second transistor (202, [15], [16]) comprising:
a plurality of second nanostructures (210B’, [31]) disposed over a second portion of the substrate (204, [22]), wherein two adjacent nanostructures of the plurality of second nanostructures (210B’, [30]) spacing are separated by a second spacing (S2, [31]) greater than the first spacing (S1, [31]), and
a second gate structure (236/250/252, [33], [41]) wrapping around each of the plurality of second nano structures (210B’, [30]);
a first isolation feature (206 of 201, [22], figures) laterally adjacent to the first portion of the substrate (204, [22]), wherein a top surface of the first isolation feature (206 of 201, [22], figures) is lower than a top surface of the first portion of the substrate (204, [22]); and
a second isolation feature (206 of 202, [22], figures) laterally adjacent to the second portion of the substrate (204, [22]), wherein a top surface of the second isolation feature (206 of 202, [22], figures) is lower than a top surface of the second portion of the substrate (204, [22]).
Regarding claim 2, Hsu discloses the semiconductor device of claim 1 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, epitaxial source/drain features (214, [26]) coupled to the plurality of first nanostructures (210B, [31]) and two opposite ends of the plurality of first nanostructures (210B, [31]) contact the epitaxial source/drain features (214, [26]).
Regarding claim 3, Hsu discloses the semiconductor device of claim 1 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, the first gate structure (242/244/252, [33], [34], [41]) comprises a first gate dielectric layer (242/244, [33], [34]) and a first conductive layer (252, [41]) over the first gate dielectric layer (242/244, [33], [34]), the second gate structure (236/250/252, [32], [34], [39], [41]) comprises a second gate dielectric layer (236/250, [32], [34], [39]) and a second conductive layer (252, [41]) over the second gate dielectric layer (236/250, [33]), and wherein a thickness of the first gate dielectric layer (242/244, [33], [34]) is different than a thickness of the second gate dielectric layer (236/250, [32], [33], [39]).
Regarding claim 4, Hsu discloses the semiconductor device of claim 3 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, the first gate dielectric layer (242/244, [33], [34]) comprises a first interfacial layer (242, [33]) and a first high- k dielectric layer (244, [34]) on the first interfacial layer (242, [33]), the second gate dielectric layer (236/250, [32], [34], [39]) comprises a second interfacial layer (236, [32]) and a second high-k dielectric layer (250, [34], [39]) on the second interfacial layer (236, [32]), and
wherein a thickness of the second interfacial layer (236, [32]) is greater than a thickness of the first interfacial layer (242, [33]).
Regarding claim 6, Hsu discloses the semiconductor device of claim 3 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, the top surface of the first isolation feature (206 of 201, [22], figures) is a curved surface.
Regarding claim 7, Hsu discloses the semiconductor device of claim 1 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, the plurality of first nanostructures (210B, [31]) has a first vertical pitch, the plurality of second nanostructures (210B’, [31]) has a second vertical pitch substantially equal to the first vertical pitch.
Regarding claim 10, Hsu discloses, in at least figures 2-3, 19A-20B, and related text, a semiconductor device, comprising:
a first protrusion (protrusion of 204 in 201, figures) extending from a substrate (204, [22]);
a plurality of first nanostructures (210B, [31]) disposed over the first protrusion (protrusion of 204 in 201, figures), wherein two adjacent nanostructures of the plurality of first nanostructures (210B, [31]) are separated by a first spacing (S1, [31]);
a first isolation feature (206 of 201, [22], figures) adjacent to the first protrusion (protrusion of 204 in 201, figures);
a first gate structure (242/244/252, [33], [34], [41]) having a first portion wrapping around each of the plurality of first nanostructures (210B, [31]) and a second portion on the first isolation feature (206 of 201, [22], figures), wherein a bottom surface of the second portion of the first gate structure (242/244/252, [33], [34], [41]) is lower than a top surface of the first protrusion (protrusion of 204 in 201, figures);
a second protrusion (protrusion of 204 in 202, figures) extending from the substrate (204, [22]);
a plurality of second nanostructures (210B’, [31]) disposed over the second protrusion (protrusion of 204 in 202, figures), wherein two adjacent nanostructures of the plurality of second nanostructures (210B’, [31]) spacing are separated by a second spacing (S2, [31]) greater than the first spacing (S1, [31]);
a second isolation feature (206 of 202, [22], figures) adjacent to the second protrusion (protrusion of 204 in 202, figures);
a second gate structure (236/250/252, [32], [34], [39], [41]) having a first portion wrapping around each of the plurality of second nanostructures (210B’, [31]) and a second portion on the second isolation feature (206 of 202, [22], figures), wherein a bottom surface of the second portion of the second gate structure (236/250/252, [32], [34], [39], [41]) is lower than a top surface of the second protrusion (protrusion of 204 in 202, figures).
Regarding claim 11, Hsu discloses the semiconductor device of claim 10 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, the first gate structure (242/244/252, [33], [34], [41]) comprises a first interfacial layer (242, [33]) having a first thickness and a first high-k dielectric layer (244, [34]) on the first interfacial layer (242, [33]) and having a second thickness, wherein the second gate structure (236/250/252, [32], [34], [39], [41]) comprises a second interfacial layer (236, [32]) having a third thickness greater than the first thickness and a second high- k dielectric layer (250, [34], [39]) on the second interfacial layer (236, [32]) and having the second thickness.
Regarding claim 12, Hsu discloses the semiconductor device of claim 11 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, a dimensional difference between the first thickness ([33]) and the third thickness ([32]) is in a range between about 2 Å and about 10 Å.
Regarding claim 13, Hsu discloses the semiconductor device of claim 11 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, the second thickness ([34]) is in a range between about 1nm and about 2nm.
Regarding claim 14, Hsu discloses the semiconductor device of claim 11 as described above.
Hsu further discloses, in at least figures 2-3, 19A-20B, and related text, the plurality of first nanostructures (210B, [31]) and the plurality of second nanostructures (210B’, [31]) has a same vertical pitch, and a thickness (T2, [30]) of a bottommost nanostructure of the plurality of second nanostructures (210B’, [31]) is less than a thickness (T1, [30]) of a bottommost nanostructure of the plurality of first nanostructures (210B, [31]).
Claim(s) 16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liaw (US 2020/0343387).
Regarding claim 16, Liaw discloses, in at least figure 7 and related text, a semiconductor device, comprising:
a first transistor comprising a plurality of first nanostructures (122, [27]) over a substrate (12, [26]);
a first structure (132 adjacent to 122, [24], figure) adjacent to the plurality of first nanostructures (122, [27]), wherein a top surface of the first structure (132 adjacent to 122, [24], figure) is above a top surface of a bottommost nanostructure of the plurality of first nanostructures (122, [27]);
a second transistor comprising a plurality of second nanostructures (142, [28]) over the substrate (12, [26]); and
a second structure (132 adjacent to 142, [24], figure) adjacent to the plurality of second nanostructures (142, [28]), wherein a top surface of the second structure (132 adjacent to 142, [24], figure) is above a top surface of a bottommost nanostructure of the plurality of second nanostructures (142, [28]),
wherein a distance between the first structure (132 adjacent to 122, [24], figure) and one of the plurality of first nanostructures (122, [27]) is different than a distance between the second structure (132 adjacent to 142, [24], figure) and one of the plurality of second nanostructures (142, [28]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2021/0066137).
Regarding claim 5, Hsu discloses the semiconductor device of claim 4 as described above.
Hsu does not explicitly disclose a thickness of each of the first and second high-k dielectric layers is in a range between about 1nm and about 2nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of each of the first and second high-k dielectric layers as claimed in claim 5 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of each of the first and second high-k dielectric layers as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- a thickness of each of the first and second high-k dielectric layers is in a range between about 1nm and about 2nm) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2021/0066137) in view of Lan (US 2021/0159311).
Regarding claim 8, Hsu discloses the semiconductor device of claim 7 as described above.
Hsu does not explicitly disclose a thickness of one the plurality of first nanostructures is less than a thickness of one of the plurality of second nanostructures.
Lan teaches, in at least figures 10E-1, 10E-2, 10E-3, and related text, the device comprising a thickness of one the plurality of first nanostructures (108e-3, [103]) is less than a thickness of one of the plurality of second nanostructures (108e-2, [103]), for the purpose of providing semiconductor device including transistors with different designs ([17]) thereby improved performance.
Hsu and Lan are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu with the specified features of Lan because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Hsu to have the thickness of one the plurality of first nanostructures being less than a thickness of one of the plurality of second nanostructures, as taught by Lan, for the purpose of providing semiconductor device including transistors with different designs ([17], Lan) thereby improved performance.
Claim(s) 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2021/0066137) in view of Liaw (US 2020/0343387).
Regarding claim 9, Hsu discloses the semiconductor device of claim 7 as described above.
Hsu does not explicitly disclose a width of one the plurality of first nanostructures is less than a width of one of the plurality of second nanostructures.
Liaw teaches, in at least figures 7-8 and related text, the device comprising a width of one the plurality of first nanostructures (122, [27]) is less than a width of one of the plurality of second nanostructures (142, [27]), for the purpose of providing flexible design integration schemes to accommodate different circuits in the same IC ([17]).
Hsu and Liaw are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Hsu to have the width of one the plurality of first nanostructures being less than a width of one of the plurality of second nanostructures, as taught by Liaw, for the purpose of providing flexible design integration schemes to accommodate different circuits in the same IC ([17], Liaw).
Regarding claim 15, Hsu discloses the semiconductor device of claim 14 as described above.
Hsu does not explicitly disclose a width of the bottommost nanostructure of the plurality of second nanostructures is less than a width of the bottommost nanostructure of the plurality of first nanostructures.
Liaw teaches, in at least figures 7-8 and related text, the device comprising a width of the bottommost nanostructure of the plurality of second nanostructures (122, [27]) is less than a width of the bottommost nanostructure of the plurality of first nanostructures (142, [27]), for the purpose of providing flexible design integration schemes to accommodate different circuits in the same IC ([17]).
Hsu and Liaw are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Hsu to have the width of the bottommost nanostructure of the plurality of second nanostructures being less than a width of the bottommost nanostructure of the plurality of first nanostructures, as taught by Liaw, for the purpose of providing flexible design integration schemes to accommodate different circuits in the same IC ([17], Liaw).
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2020/0343387) in view of Lan (US 2021/0159311).
Regarding claim 17, Liaw discloses the semiconductor device of claim 16 as described above.
Liaw does not explicitly disclose the first structure comprises a silicon-containing material.
Lan teaches, in at least figurse 10E-2, 10E-3, and related text, the device comprising the first structure (120/122, [34], [35]) comprises a silicon-containing material, for the purpose of providing semiconductor device including transistors with different designs ([17]) thereby improved performance.
Liaw and Lan are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw with the specified features of Lan because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Liaw to have the first structure comprising a silicon-containing material, as taught by Lan, for the purpose of providing semiconductor device including transistors with different designs ([17], Lan) thereby improved performance.
Regarding claim 18, Liaw discloses the semiconductor device of claim 16 as described above.
Liaw does not explicitly disclose the first structure comprises: a first dielectric layer; a second dielectric layer extending along sidewall and bottom surface of the first dielectric layer.
Lan teaches, in at least figurse 10E-2, 10E-3, and related text, the device comprising the first structure (120/122, [34], [35]) comprises: a first dielectric layer (120, [34]); a second dielectric layer (122, [35]) extending along sidewall and bottom surface of the first dielectric layer (120, [34]), for the purpose of providing semiconductor device including transistors with different designs ([17]) thereby improved performance.
Liaw and Lan are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw with the specified features of Lan because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Liaw to have the first structure comprising: a first dielectric layer; a second dielectric layer extending along sidewall and bottom surface of the first dielectric layer, as taught by Lan, for the purpose of providing semiconductor device including transistors with different designs ([17], Lan) thereby improved performance.
Regarding claim 19, Liaw discloses the semiconductor device of claim 16 as described above.
Liaw does not explicitly disclose an isolation feature adjacent to a portion of the substrate disposed under the plurality of first nanostructures, wherein a top surface of the isolation feature is lower than a top surface of the portion of the substrate, and wherein the first structure is disposed over the isolation feature.
Lan teaches, in at least figurse 10E-2, 10E-3, and related text, the device comprising an isolation feature (114, [27]) adjacent to a portion of the substrate (102, [27]) disposed under the plurality of first nanostructures (108e-3, [103]), wherein a top surface of the isolation feature (114, [27]) is lower than a top surface of the portion of the substrate (102, [27]), and wherein the first structure (120/122, [34], [35]) is disposed over the isolation feature (114, [27]), for the purpose of providing semiconductor device including transistors with different designs ([17]) thereby improved performance.
Liaw and Lan are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw with the specified features of Lan because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Liaw to have the isolation feature adjacent to a portion of the substrate disposed under the plurality of first nanostructures, wherein a top surface of the isolation feature is lower than a top surface of the portion of the substrate, and wherein the first structure is disposed over the isolation feature, as taught by Lan, for the purpose of providing semiconductor device including transistors with different designs ([17], Lan) thereby improved performance.
Regarding claim 20, Liaw discloses the semiconductor device of claim 16 as described above.
Liaw does not explicitly disclose a vertical pitch of the plurality of first nanostructures is substantially equal to a vertical pitch of the plurality of second nanostructures, and a thickness of one of the plurality of first nanostructures is different than a thickness of one of the plurality of second nanostructures.
Lan teaches, in at least figurse 10E-2, 10E-3, and related text, the device comprising a vertical pitch of the plurality of first nanostructures (108e-3, [103]) is substantially equal to a vertical pitch of the plurality of second nanostructures (108e-2, [103]), and a thickness of one of the plurality of first nanostructures (108e-3, [103]) is different than a thickness of one of the plurality of second nanostructures (108e-2, [103]), for the purpose of providing semiconductor device including transistors with different designs ([17]) thereby improved performance.
Liaw and Lan are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw with the specified features of Lan because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Liaw to have the vertical pitch of the plurality of first nanostructures being substantially equal to a vertical pitch of the plurality of second nanostructures, and the thickness of one of the plurality of first nanostructures being different than a thickness of one of the plurality of second nanostructures, as taught by Lan, for the purpose of providing semiconductor device including transistors with different designs ([17], Lan) thereby improved performance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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