DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested: “A SEMICONDUCTOR DEVICE HAVING MULTIPLE SOUCE/DRAIN EPITAXIAL LAYERS AND METHOD OF MANUFACTURING THEREOF.”
If Applicant does not agree with the suggested title above, Applicant must provide a new title that clearly reflects the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US Pub. 2018/0151378; hereinafter “Huang”) in view of Mochizuki et al. (US Pat. 10,453,824; hereinafter “Mochizuki”).
Regarding Claim 17, Huang discloses a semiconductor device comprising: an n-type field effect transistor (FET) (n-type finFET; page 2, paragraph 43); and a p-type FET (p-type finFET; page 2, paragraph 43), wherein: each of the n-type FET and the p-type FET comprises: semiconductor strips 52 disposed over a substrate 50 (page 2, paragraph 45); a source/drain epitaxial layer (82, 84) (page 5, paragraph 62) in contact with the semiconductor strips 52 (see fig. 24C); a gate dielectric layer (92, 96) (page 7, paragraph 91) disposed on the semiconductor strips 52 (see fig. 25A); a gate electrode layer (94, 98) (page 7, paragraph 92) disposed on the gate dielectric layer (92, 96) (see figs. 25A and 25B); wherein the source/drain epitaxial layer of the n-type FET 82 (page 5, paragraph 63) includes multiple SiP layers 45 having different P contents (the epitaxial source/drain region 82 may include SiP; page 5, paragraph 67; and epitaxy layers 45 may also include a lower layer and un upper layer with different material compositions divided by a dashed lines 43; page 5, paragraph 70; see figs. 15B and 25B), the source/drain epitaxial layer of the p-type FET 84 (page 6, paragraph 74) includes multiple SiGe layers 57 having different Ge contents (epitaxy layers 57 may also include a lower layer and an upper layer with different germanium percentages divided by dashed lines 63; page 6, paragraph 83; see figs. 20B and 25B).
Huang fails to disclose explicitly wherein a stack of semiconductor nanosheets disposed over the substrate; the source/drain epitaxial layer in contact with the semiconductor nanosheets; the gate dielectric layer wrapping around each channel region of the semiconductor nanosheets; the gate electrode layer disposed over the gate dielectric layer and wrapping around each channel region; insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent semiconductor nanosheets, the gate electrode layer, and the source/drain epitaxial layer; and a lowermost SiP layer and a lowermost SiGe layer are not in contact with a bottommost one of the insulating spacers.
However, Mochizuki discloses a gate-all-around (GAA) FET device comprising: a stack of silicon nanosheet layers (107a-107c) over a substrate 102 (col. 4, lines 45-67; see fig. 10); epitaxially grown of source/drain regions 165 (col. 8, lines 4-18) in contact with the silicon nanosheet layers (107a-107c) (see fig. 10); a gate dielectric layer 185 (col. 9, lines 4-19) wrapping around each channel region of silicon nanosheet layers (107a-107c) (see fig. 10); a gate region 180 (col. 9, lines 19-36) disposed over the gate dielectric layer 185 and wrapping around each channel region (see fig. 10); inner spacer layers 150 (col. 6, lines 56-67) disposed in spaces (see fig. 10), respectively, the spaces being defined by adjacent silicon nanosheet layers (107a-107c), the gate region 180, and the source/drain region 165 (see fig. 10); and wherein the source/drain regions 165 further include lower epitaxial layers 160 (col. 7, lines 30-47) that are not in contact with a bottommost one of the inner spacer layers 150 (see fig. 10).
Huang also discloses lower epitaxy layers (39, 51) in the epitaxial source/drain regions (82, 84) (see fig. 25B). Accordingly, the lower epitaxy layers (39, 51) disclosed in Huang may be formed in the same manner as the lower epitaxial layer 160 disclosed in Mochizuki for a GAA structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a stack of semiconductor nanosheets, a gate structure wrapping around nanowire channels, inner spacers, and lower epitaxial layers, as taught by Mochizuki, in order to obtain a gate-all-around structure.
Regarding Claim 20, Huang discloses wherein a bottom of the lowermost SiP and SiGe layers (39, 51) have a V-shape or a U-shape (see fig. 25B).
Allowable Subject Matter
Claims 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 18 recites the multiple SiP layers include a second epitaxial layer having a higher P content than the lowermost SiP layer disposed over the lowermost SiP layer, a third epitaxial layer having a higher P content than the second epitaxial layer disposed over the second epitaxial layer, and a fourth epitaxial layer having a lower P content than the third epitaxial layer disposed over the third epitaxial layer.
Claim 19 recites the multiple SiGe layers include a second SiGe layer having a higher Ge content than the lowermost SiGe layer disposed over the lowermost SiGe layer, a third second SiGe layer having a higher Ge content than the second SiGe layer disposed over the second SiGe layer, and fourth SiGe layer having a lower Ge content than the third SiGe layer disposed over the second SiGe layer.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 1-16 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites the doped epitaxial layer comprises: a first doped epitaxial layer disposed over the non-doped base epitaxial layer; a second doped epitaxial layer having a higher dopant content than the first doped epitaxial layer disposed over the first doped epitaxial layer; and a third doped epitaxial layer having a lower dopant content than the second doped epitaxial layer disposed over the second epitaxial layer.
Claim 9 recites the source/drain epitaxial layer comprises: a first doped epitaxial layer, which is not in contact with a bottommost one of the insulating spacers; a second doped epitaxial layer having a higher dopant content than the first doped epitaxial layer disposed over the first doped epitaxial layer; a third doped epitaxial layer having a higher dopant content than the second doped epitaxial layer disposed over the second doped epitaxial layer; and a fourth doped epitaxial layer having a lower dopant content than the third doped epitaxial layer disposed over the third epitaxial layer.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-8 and 10-16 variously depend from claim 1 or 9, so they are allowed for the same reason.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 and 18-20 of U.S. Patent No. 12,062,580 (hereinafter “Pat-580”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-580 discloses all the claimed limitations. See rejections below.
Regarding Claim 17, Pat-580 discloses a semiconductor device comprising: an n-type field effect transistor (FET) (see claim 16); and a p-type FET (see claim 16), wherein: each of the n-type FET and the p-type FET comprises: a stack of semiconductor nanosheets disposed over a substrate (see claim 16); a source/drain epitaxial layer in contact with the semiconductor nanosheets (see claim 16); a gate dielectric layer wrapping around each channel region of the semiconductor nanosheets (see claim 16); a gate electrode layer disposed over the gate dielectric layer and wrapping around each channel region (see claim 16); and insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent semiconductor nanosheets, the gate electrode layer, and the source/drain epitaxial layer (see claim 16), wherein the source/drain epitaxial layer of the n-type FET includes multiple SiP layers having different P contents (see claim 16), the source/drain epitaxial layer of the p-type FET includes multiple SiGe layers having different Ge contents (see claim 16), and a lowermost SiP layer and a lowermost SiGe layer are not in contact with a bottommost one of the insulating spacers (non-doped base epitaxial layer is not in contact with a bottommost one of the insulating spacers; see claim 16).
Regarding Claim 18, Pat-580 discloses wherein the multiple SiP layers include a second epitaxial layer (a first epitaxial layer; see claim 18) having a higher P content than the lowermost SiP layer (non-doped base epitaxial layer; see claim 16) disposed over the lowermost SiP layer (see claim 16), a third epitaxial layer (a second epitaxial layer; see claim 18) having a higher P content than the second epitaxial layer disposed over the second epitaxial layer (see claim 18), and a fourth epitaxial layer (a third epitaxial layer; see claim 18) having a lower P content than the third epitaxial layer disposed over the third epitaxial layer (see claim 18).
Regarding Claim 19, Pat-580 discloses wherein the multiple SiGe layers include a second SiGe layer (a first SiGe layer; see claim 19) having a higher Ge content than the lowermost SiGe layer (a non-doped base epitaxial layer; see claim 19) disposed over the lowermost SiGe layer (see claim 19), a third second SiGe layer (a second SiGe layer; see claim 19) having a higher Ge content than the second SiGe layer disposed over the second SiGe layer (see claim 19), and fourth SiGe layer (a third SiGe layer; see claim 19) having a lower Ge content than the third SiGe layer disposed over the second SiGe layer (see claim 19).
Regarding Claim 20, Pat-580 discloses wherein a bottom of the lowermost SiP and SiGe layers (non-doped base epitaxial layer; see claim 16) have a V-shape or a U-shape (see claim 20).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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/CHEUNG LEE/
Primary Examiner, Art Unit 2812 August 22, 2026
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