DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/28/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 5-20 of U.S. Patent No. 12,051,736. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 10 and 14 are broader than, and anticipated by claims 1, 11 and 14 of patent no. 12,051,736. See table below for claim to claim matching. Claims 2-9,11-13 and 15-20 are also anticipated by claims 2-10, 12-13 and 15-20 of patent no. 12,051,736.
Current Application
Patent No. 12,051,736
1. A device, comprising: a nanostructure channel; an inner spacer above or below the nanostructure channel; a gate structure abutting the nanostructure channel and the inner spacer; and a liner layer between the inner spacer and the gate structure, the liner layer and the nanostructure channel include substantially the same material.
1. A device, comprising: nanostructure channel
2. The device of claim 1, wherein an upper surface of the liner layer is substantially coplanar with a lower surface of the nanostructure channel.
2. The device of claim 1, wherein an upper surface of the liner layer is substantially coplanar with a lower surface of the first nanostructure channel.
3. The device of claim 1, wherein a lower surface of the liner layer is substantially coplanar with an upper surface of the nanostructure channel.
2. The device of claim 1, wherein an upper surface of the liner layer is substantially coplanar with a lower surface of the first nanostructure channel.
4. The device of claim 1, wherein the gate structure includes an interfacial layer in contact with the nanostructure channel and the liner layer.
5. The device of claim 1, wherein the gate structure includes an interfacial layer in contact with the first nanostructure channel,
5. The device of claim 4, wherein a portion of the interfacial layer in contact with the liner layer has a different material composition than a portion of the interfacial layer in contact with the nanostructure channel.
6. The device of claim 5, wherein a portion of the interfacial layer in contact with the liner layer has a different material composition than a portion of the interfacial layer in contact with the first nanostructure channel.
6. The device of claim 1, wherein end portions of the nanostructure channel are thinner in a vertical direction than a middle portion of the nanostructure channel.
7. The device of claim 1, wherein end portions of the first nanostructure channel are thinner in a vertical direction than a middle portion of the first nanostructure channel.
7. The device of claim 6, wherein an upper surface of the liner layer is at a different level than a lower surface of the nanostructure channel.
8. The device of claim 7, wherein an upper surface of the liner layer is at a different level than a lower surface of the first nanostructure channel.
8. The device of claim 1, wherein the liner layer has a thickness in a range of about 1 nanometer (nm) to about 2 nm.
9. The device of claim 1, wherein the liner layer has a thickness in a range of about 1 nanometer (nm) to about 2 nm.
9. The device of claim 1, further comprising a source/drain region in contact with the nanostructure channel, the liner layer, and the inner spacer.
10. The device of claim 1, further comprising a source/drain region in contact with the first nanostructure channel, the liner layer and the inner spacer.
10. A device comprising: a semiconductor nanosheet; a first inner spacer above the semiconductor nanosheet; a second inner spacer below the semiconductor nanosheet; a first liner layer between the semiconductor nanosheet and the first inner spacer; and a second liner layer between the semiconductor nanosheet and the second inner spacer, wherein each of the first liner layer and the second liner layer includes a semiconductive material.
11. A device comprising: a semiconductor nanosheet
11. The device of claim 10, further comprising: a gate structure region above the semiconductor nanosheet, the gate structure region having substantially the same height as the first inner spacer.
12. The device of claim 11, further comprising: a gate structure region above the semiconductor nanosheet, the gate structure region having substantially the same height as the first inner spacer.
12. The device of claim 10, wherein each of the first and second liner layers has a thickness in a range of about 1 nanometer (nm) to about 2 nm.
9. The device of claim 1, wherein the liner layer has a thickness in a range of about 1 nanometer (nm) to about 2 nm.
13. The device of claim 10, further comprising: a source/drain region in contact with the semiconductor nanosheet, the first and second inner spacers, and the first and second liner layers.
13. The device of claim 11, further comprising: a source/drain region in contact with the semiconductor nanosheet, the first and second inner spacers, and the first and second liner layers.
14. A method, comprising: forming a vertical stack of alternating first nanosheets and second nanosheets over a substrate; forming recesses by removing end portions of the second nanosheets; and forming a liner layer in the recesses, including: depositing a semiconductive material in the recesses; and forming an inner spacer in each of the recesses.
14. A method, comprising: forming a vertical stack of alternating first nanosheets and second nanosheets over a substrate; forming recesses by removing end portions of the second nanosheets; forming a liner layer in the recesses, including: depositing a semiconductive material in the recesses;
15. The method of claim 14, further comprising: expanding the recesses by trimming end portions of the first nanosheets prior to forming the liner layer.
15. The method of claim 14, further comprising: expanding the recesses by trimming end portions of the first nanosheets prior to forming the liner layer.
16. The method of claim 14, further comprising: forming gaps between the first nanosheets by removing the second nanosheets; and forming a gate structure in the gaps.
16. The method of claim 14, further comprising: forming gaps between the first nanosheets by removing the second nanosheets; and forming a gate structure in the gaps.
17. The method of claim 16, wherein the forming a gate structure includes: forming an interfacial layer on surfaces of the first nanosheets and the liner layer exposed by the gaps.
17. The method of claim 16, wherein the forming a gate structure includes: forming an interfacial layer on surfaces of the first nanosheets and the liner layer exposed by the gaps.
18. The method of claim 17, wherein the forming a gate structure includes: forming a gate dielectric layer on the interfacial layer; and forming a metal fill layer on the gate dielectric layer.
18. The method of claim 17, wherein the forming a gate structure includes: forming a gate dielectric layer on the interfacial layer; and forming a metal fill layer on the gate dielectric layer.
19. The method of claim 18, further comprising: forming a source/drain region in contact with the first nanosheets, the liner layer, and the inner spacer.
19. The method of claim 18, further comprising: forming a source/drain region in contact with the first nanosheets, the liner layer, and the inner spacer.
20. The method of claim 14, wherein the liner layer has a thickness in a range of about 1 nanometer (nm) to about 2 nm.
20. The method of claim 14, wherein the liner layer has a thickness in a range of about 1 nanometer (nm) to about 2 nm.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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