DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/01/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 and claim 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "TSVs of a first one of the third plurality of dies" in line 5. There is insufficient antecedent basis for this limitation in the claim. Note: all dependent claims necessarily inherit the indefiniteness of the claims from which they depend.
Claim 14 recites the limitation " TSVs of a first one of the fourth plurality of dies" in line 4. There is insufficient antecedent basis for this limitation in the claim. Note: all dependent claims necessarily inherit the indefiniteness of the claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (PG Pub 2022/0157732; hereinafter Tsai) and Su et al. (PG Pub 2020/0365489; hereinafter Su).
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Regarding claim 7, refer to the Examiner’s modified mark-up of Fig. 3 provided above, Tsai teaches a method of forming a semiconductor device (see claim limitations below), comprising:
forming a first wafer scale redistribution structure 23, wherein the first wafer scale redistribution structure comprises a first plurality of conductive features (230m, 230v) and a first plurality of dielectric layers 232; bonding a first plurality of dies (3051, 3061) to the first wafer scale redistribution structure at a first side (top side), wherein the first plurality of dies is electrically connected to corresponding ones of the first plurality of conductive features (see Fig. 3), and encapsulating the first plurality of dies with a first encapsulant 302;
forming a second wafer scale redistribution structure 33 on the first plurality of dies and the first encapsulant (see modified Fig. 3), wherein the second wafer scale redistribution structure comprises a second plurality of conductive features (330m, 330v) and a second plurality of dielectric layers 332, and
bonding a second plurality of dies annotated “die-2”; in Fig. 3 above) to the second wafer scale redistribution structure, wherein the second plurality of dies is electrically connected to corresponding ones of the second plurality of conductive features (see Fig. 3); encapsulating the second plurality of dies with a second encapsulant (annotated “encap”);
bonding a third plurality of dies (2051,2061) to the first wafer scale redistribution structure at a second side (bottom side) opposite to the first side (see Fig. 3), wherein the third plurality of dies is electrically connected to corresponding ones of the first plurality of conductive features (thru 204; see Fig. 3); and encapsulating the third plurality of dies with a third encapsulant 102 (see Fig. 3).
Although, Tsai teaches a plurality of die structures (e.g. 20,30) are formed over redistribution structures (e.g. 13,23); wherein Fig. 3 only shows two die structures (e.g. 20, 30) formed over two redistribution structures respectively (e.g. 13,23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the number of paired die structures and redistribution structures to create a more robust package. Furthermore, it has been held that the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960))
Although, Tsai teaches the first one of the first plurality of dies are electrically connected to corresponding ones of the second plurality of conductive features (through vias 304), he does not explicitly teach a first one of the first plurality of dies comprises through substrate vias (TSVs); and wherein the TSVs of the first one of the first plurality of dies are electrically connected to corresponding ones of the second plurality of conductive features.
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In the same field of endeavor, refer to Fig. 2G-provided above, Su teaches an electronic package comprising: a first one (e.g. 21-L) of a first plurality of dies 21 comprises through substrate vias (TSVs) 210; and wherein the TSVs of the first one of the first plurality of dies are electrically connected to corresponding ones of a second plurality of conductive features 261 (see Fig. 2G”).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a first plurality of dies comprises through substrate vias, as taught by Su, to provide electrical communication to a wiring board, the die and the redistribution layer.
Regarding claim 12, refer to the figures cited above, in the combination of Tsai and Su, Tsai teaches forming a plurality of through dielectric vias (TDVs) 204 at the second side (bottom side) of the first wafer scale redistribution structure 23 beside the third plurality of dies (2051,2061), wherein the plurality of TDVs is electrically connected to corresponding ones of the first plurality of conductive features (see Fig. 3); and encapsulating the plurality of TDVs with the third encapsulant 202 (see Fig. 3).
Regarding claim 13, refer to the figures cited above, in the combination of Tsai and Su, Tsai teaches forming a third wafer scale redistribution structure 13 on the third plurality of dies (2051,2061) and the third encapsulant 202, wherein the third wafer scale redistribution structure comprises a third plurality of conductive features (130m,130v) and a third plurality of dielectric layers 132, and wherein TSVs 2056 of a first one of the third plurality of dies 204 are electrically connected to corresponding ones of the third plurality of conductive features (see Fig. 3); and bonding a fourth plurality of dies (1051,1061) to the third wafer scale redistribution structure (see Fig. 3).
Regarding claim 14, refer to the figures cited above, in the combination of Tsai and Su, Tsai teaches forming a passivation layer 42 and a plurality of conductive pads 40 on the fourth plurality of dies (1051, 1061), wherein the plurality of conductive pads extends through the passivation layer (see Fig. 3), and wherein TSVs 1056 of a first one of the fourth plurality of dies are electrically connected to corresponding ones of the plurality of conductive pads (thru 104).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai and Su, as applied to claim 7 above, and further in view of Chen et al. (PG Pub 2021/0375819; hereinafter Chen).
Regarding claim 8, refer to the figures cited above, in the combination of Tsai and Su, Although Tsai teaches the first plurality of dies (3051,3061) is bonded to the first wafer scale redistribution structure 23 through bond pads; and wherein the third plurality of dies (2051,2061) is bonded to the first wafer scale redistribution structure through bond pads (see Fig. 3). Tsai does not teach the explicit bonding between the plurality of dies and the redistribution structure(s) is through a metal-to-metal bonding.
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In the same field of endeavor, refer to Fig. 7 provided above, Chen teaches a semiconductor package comprising: bonding chips 46 to a redistribution structure 22 through hybrid bonding; wherein bond pads 54 are bonded to bond pads 45 through metal-to-metal direct bonding (para [0024]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the hybrid bonding as taught by Chen, to form a stronger bond between the dies and the redistribution structure.
Allowable Subject Matter
3. Claims 1-6 and 15-20 are allowable.
Claims 9-11 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 1, forming a first interconnect on a first wafer substrate; coupling a first plurality of dies to a first surface of the first interconnect with metal-metal bonds; encapsulating the first plurality of dies with a first encapsulant; attaching a second wafer substrate to surfaces of the first plurality of dies and the first encapsulant; removing the first wafer substrate; coupling a second plurality of dies to a second surface of the first interconnect with metal-metal bonds, wherein the second surface of the first interconnect is opposite to the first surface of the first interconnect; and encapsulating the second plurality of dies with a second encapsulant. Claims 2-6 would be allowable, because they depend on allowable claim 1.
Claim 9 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 9 attaching a support substrate to surfaces of the second plurality of dies and the second encapsulant. Claims 10-11 would be allowable, because they depend on allowable claim 9.
Claim 15 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 15, forming a first redistribution structure on a first side of a wafer, wherein the first redistribution structure comprises a first plurality of conductive features and a first plurality of dielectric layers, wherein the wafer comprises a plurality of conductive vias electrically connected to corresponding ones of the first plurality of conductive features; bonding a first plurality of dies to the first redistribution structure; encapsulating the first plurality of dies with a first encapsulant; and thinning a second side of the wafer to expose the plurality of conductive vias at the second side. Claims 16-20 would be allowable, because they depend on allowable claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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