Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 objected to because of the following informalities: claim 5 recites the phrase “comprises a an isolation trench…” which has two indefinite articles and so the first, “a,” should be removed. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the copper isolation trench" in line 1. There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, examiner will interpret the claim without the term “copper” so that it refers to the “isolation trench” of claim 5.
Claim 7 rejected as being dependent to a claim rejected under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 8-10, 15-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US20110241000A1, hereinafter Choi).
Regarding claim 1, Choi discloses a semiconductor device, comprising:
a display pixel array comprising a plurality of display pixels (Fig. 14 red, blue, and green pixels R/B/G),
wherein a display pixel, of the plurality of display pixels, comprises:
a first electrode (Fig. 14 electrode layer 50c);
a dielectric region above the first electrode (Fig. 14 intermediate layer 70);
a light generation film stack above the dielectric region (Fig. 14 organic light emitting layers 75 disposed above reflective layer 52);
a second electrode above the light generation film stack (Fig. 14 second electrode layer 80); and
an isolation structure laterally surrounding the dielectric region (Fig. 14 pixel defining layer 60 laterally surrounds intermediate layer 70 in each of the pixels).
Regarding claim 3, Choi discloses the semiconductor device of claim 1,
wherein a bottom surface of the isolation structure is on top of the first electrode (Fig. 14 the left portion of rightmost pixel defining layer 60 is on top of electrode 50c).
Regarding claim 8, Choi discloses a semiconductor device, comprising:
a semiconductor substrate (Fig. 14 substrate 10);
a plurality of integrated circuit devices in the semiconductor substrate (Fig. 14 plurality of TFTs on substrate 10);
an interconnect layer above the semiconductor substrate (Fig. 14 planarization layer 30 comprises a plurality of interconnects to electrode layers 50a/50b/50c); and
a display pixel array, above the interconnect layer, comprising a plurality of display pixels (Fig. 14 plurality of pixels as represented by electrode layers 50a/50b/50c disposed above planarization layer 30),
wherein a display pixel, of the plurality of display pixels, comprises a plurality of subpixels,
wherein each subpixel of the plurality of subpixels comprises:
a bottom electrode (Fig. 14 metal layer 51);
a resonance region above the bottom electrode (Fig. 14, par. 50 reflective layers 52 which “acts as a reflective mirror in an optical resonance structure”);
a light generation film stack above the resonance region (Fig. 14 organic light emitting layers 75 disposed above reflective layer 52);
a top electrode above the light generation film stack (Fig. 14 second electrode layer 80); and
an isolation structure laterally surrounding the resonance region (Fig. 14 pixel defining layer 60 laterally surrounds reflective layer 52 in each of the pixels).
Regarding claim 9, Choi discloses the semiconductor device of claim 8,
wherein a first isolation structure of a first subpixel of the plurality of subpixels has a first vertical thickness (Fig. 14 rightmost pixel defining layer 60 has a first vertical thickness);
wherein a second isolation structure of a second subpixel of the plurality of subpixels has a second vertical thickness (Fig. 14 second from rightmost pixel defining layer 60 has a second vertical thickness); and
wherein the first vertical thickness and the second vertical thickness are approximately a same thickness (Fig. 14 rightmost pixel defining layer 60 and second from rightmost pixel defining layer 60 have approximately the same thickness).
Regarding claim 10, Choi discloses the semiconductor device of claim 8,
wherein a first bottom electrode of a first subpixel of the plurality of subpixels has a first vertical thickness (Fig. 14 electrode 50c has a first thickness); wherein
a second bottom electrode of a second subpixel of the plurality of subpixels has a second vertical thickness (Fig. 14 electrode 50a has a second thickness); and
wherein the first vertical thickness and the second vertical thickness are different thicknesses (Fig. 14 the thickness of electrode 50a is different than the thickness of electrode 50c).
Regarding claim 15, Choi discloses a method, comprising:
forming, above an interconnect layer of a semiconductor device (Fig. 14 planarization layer 30 comprises a plurality of interconnects to electrode layers 50a/50b/50c), a first electrode of a first subpixel of a display pixel of a display pixel array of the semiconductor device (Fig. 14 metal layer 51 formed in pixel as represented by electrode layers 50c);
forming, above the interconnect layer, a second electrode of a second subpixel of the display pixel (Fig. 14 metal layer 51 formed in pixel as represented by electrode layers 50b);
forming a dielectric layer over the first electrode and the second electrode (Fig. 14 pixel defining layer 60 disposed over electrodes 50b/50c);
forming, in the dielectric layer, a first closed-loop recess around a first perimeter of the first electrode (Fig. 14 the pixel as represented by electrode 50c is disposed in a first closed-loop recess defined by pixel defining layer 60);
forming, in the dielectric layer, a second closed-loop recess around a second perimeter of the second electrode (Fig. 14 the pixel as represented by electrode 50b is disposed in a second closed-loop recess defined by pixel defining layer 60);
forming a first closed-loop isolation structure in the first closed-loop recess,
wherein the first closed-loop isolation structure defines a first dielectric resonance cavity above the first electrode (Fig. 14, par. 50 pixel defining layer 60 disposed around and defines reflective layer 52 in electrode 50c which “which “acts as a reflective mirror in an optical resonance structure”); and
forming a second closed-loop isolation structure in the second closed-loop recess,
wherein the second closed-loop isolation structure defines a second dielectric resonance cavity above the first electrode (Fig. 14, par. 50 pixel defining layer 60 disposed around and defines reflective layer 52 in electrode 50b which “which “acts as a reflective mirror in an optical resonance structure”).
Regarding claim 16, Choi discloses the method of claim 15,
wherein forming the first electrode comprises forming the first electrode such that a first top surface of the first electrode is located at a first height in the semiconductor device (Fig. 14 electrode 50a has a first thickness); and
wherein forming the second electrode comprises forming the second electrode such that a second top surface of the second electrode is located at a second height in the semiconductor device (Fig. 14 electrode 50c has a second thickness),
wherein the first height is greater than the second height (Fig. 14 thickness of electrode 50a is greater than the thickness of electrode 50c).
Regarding claim 17, Choi discloses the method of claim 15,
wherein forming the first closed-loop recess comprises forming the first closed-loop recess to a first depth in the dielectric layer (Fig. 14 rightmost/second from rightmost pixel defining layer 60 has a first vertical thickness); and
wherein forming the second closed-loop recess comprises forming the second closed-loop recess to a second depth in the dielectric layer (Fig. 14 second/third from rightmost pixel defining layer 60 have a second vertical thickness),
wherein the first depth and the second depth are approximately a same depth (Fig. 14 rightmost pixel defining layer 60 and second from rightmost pixel defining layer 60 have approximately the same thickness).
Regarding claim 19, Choi discloses the method of claim 15, further comprising:
planarizing the first closed-loop isolation structure and the second closed-loop isolation structure such that a first top surface of the first closed-loop isolation structure and a second top surface of the second closed-loop isolation structure are approximately co-planar (Fig. 14 all of the pixel defining layers 60 are approximately co-planar).
Regarding claim 20, Choi discloses the method of claim 15, further comprising:
providing a first organic light generation film stack above the first dielectric resonance cavity (Fig. 14 organic light emitting layer 75 above electrode layers 50c); and
providing a second organic light generation film stack above the second dielectric resonance cavity (Fig. 14 organic light emitting layer 75 above electrode layers 50b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US20110241000A1).
Regarding claim 4, Choi discloses the semiconductor device of claim 1,
wherein a vertical thickness of the isolation structure is approximately equal to a thickness of the dielectric region (While Choi fig. 14 does not teach a vertical thickness of pixel defining layer 60 as being approximately equal to a thickness of intermediate layer 70, the only difference between Choi and the claimed invention is a relative recitation of dimensions. As nothing within the disclosure indicates that a device having an isolation structure with the claimed dimensions would perform differently than Choi, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore change the thickness of pixel defining layer 60 to be approximately equal to a thickness of intermediate layer 70, see MPEP 2144.04(VI)(B)).
Regarding claim 11, Choi teaches the semiconductor device of claim 8,
wherein a first bottom surface of a first resonance region of a first subpixel of the plurality of subpixels is located closer to the interconnect layer than a second bottom surface of a second resonance region of a second subpixel of the plurality of subpixels (While the bottom surfaces of Choi’s reflective layers 52 in the blue and green pixels are both located the same distance from planarization layer 30, the primary function of the reflective layers is to act as a reflective mirror in an optical resonance structure, see par. 50. A rearrangement of the reflective layer 52 in the green pixel to be located further away from the planarization layer would not provide any new or unexpected results as the primary function of acting as a reflective mirror in an optical resonance structure is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange the reflective layer 52 in the green pixel to be located further away from the planarization layer, see MPEP 2144.04(VI)(B)).
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US20110241000A1) in view of Chu et al. (US20150362165A1, hereinafter Chu).
Regarding claim 5, Choi teaches the semiconductor device of claim 1,
wherein the isolation structure comprises an isolation trench, around the dielectric region (Fig. 14 pixel defining layer 60 disposed in a trench surrounding electrode 50c).
Choi does not appear to teach
wherein the isolation structure comprises one or more metal-containing materials.
Chu teaches
wherein the isolation structure comprises one or more metal-containing materials (Fig. 37 isolation region between adjacent subpixels comprises BM array which par. 73 teaches “could be patterned by plating thick metal layers”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi with the teachings of Chu because the addition of Chu’s BM array “help[s] to stop the light escaping to the neighbor adjacent sub-pixel unit region to prevent the crosstalk effect” (Chu par. 73).
Allowable Subject Matter
Claims 2, 12-14, and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6-7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the closest prior art (US20110241000A1, US20100051973A1, US20190165026A1) teaches the semiconductor device of claim 1.
However, the closest prior art does not teach in combination with the other claimed elements
wherein a bottom surface of the isolation structure extends into the first electrode.
Examiner notes that while there are embodiments within the prior art, see Choi figs. 13-14, that teach an isolation structure 60 that extends between electrodes of adjacent pixels, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that a bottom surface of the isolation structure extends into the first electrode in addition with the other limitations of the independent claim.
Examiner additionally notes par. 46 of the specification which describes the difference in performance associated with the allowable subject matter.
Regarding claim 6 and its dependent claim, the closest prior art (US20110241000A1, US20100051973A1, US20190165026A1) teaches the semiconductor device of claim 5.
However, the closest prior art does not teach in combination with the other claimed elements
wherein the isolation structure further comprises one or more liners on sidewalls and on a bottom surface of the isolation trench.
Additionally, the closest prior art does not teach the above in combination with the further limitations of the dependent claim.
Regarding claim 12, the closest prior art (US20110241000A1, US20100051973A1, US20190165026A1) teaches the semiconductor device of claim 11.
However, the closest prior art does not teach in combination with the other claimed elements
wherein a third top surface of a first isolation structure of the first subpixel is approximately co-planar with the first bottom surface of the first resonance region; and
wherein a fourth top surface of a second isolation structure of the second subpixel is located closer to the interconnect layer than the second bottom surface of the second resonance region.
Regarding claim 13, the closest prior art (US20110241000A1, US20100051973A1, US20190165026A1) teaches the semiconductor device of claim 8,
wherein a first bottom electrode of a first subpixel of the plurality of subpixels comprises a first metal layer (Choi fig. 14 green pixel electrode 50b conductive layer 53);
wherein a second bottom electrode of a second subpixel of the plurality of subpixels comprises:
a second metal layer (Choi fig. 14 blue pixel electrode 50c comprises reflective layer 52);
a third metal layer on the metal nitride layer (Choi fig. 14 blue pixel 50c comprises conductive layer 53);
wherein a first isolation ring of the first subpixel is located on a top surface of the first metal layer (Choi fig. 14 rightmost pixel defining layer 60 is located on a top surface of blue electrode 50c).
However, the closest prior art does not teach in combination with the other claimed elements
a metal nitride layer on the second metal layer; and
wherein a second metal isolation structure of the second subpixel is located on the second metal layer and extends through the metal nitride layer and the third metal layer.
Examiner notes that while there are embodiments within the prior art, see Kobayashi par. 92, that teach the introduction of a silicon nitride layer on a pixel electrode in order to maintain a constant thickness among a variety of pixels, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that a metal nitride layer is disposed on the second metal layer second metal and the isolation structure of the second subpixel is located on the second metal layer and extends through the metal nitride layer and the third metal layer in addition with the other limitations of the independent claim.
Examiner additionally notes par. 61 of the specification which describes the difference in performance associated with the allowable subject matter.
Regarding claim 14, the closest prior art (US20110241000A1, US20100051973A1, US20190165026A1) teaches the semiconductor device of claim 8,
wherein a first bottom electrode of a first subpixel of the plurality of subpixels comprises:
a first plurality of metal layers (Choi fig. 14 green electrode 50b comprises a plurality of metal layers 51, 52, 53, 55); and
wherein a second bottom electrode of a second subpixel of the plurality of subpixels comprises:
a second plurality of metal layers (Choi fig. 14 green electrode 50c comprises a plurality of metal layers 51, 52, 53); and
wherein a first quantity of metal layers in the first plurality of metal layers is greater than a second quantity of metal layers in the second plurality of metal layers (Choi fig. 14 green electrode 50b comprises 4 metal layers and blue electrode 50c comprises 3 metal layers).
However, the closest prior art does not teach in combination with the other claimed elements
wherein a first bottom electrode of a first subpixel of the plurality of subpixels comprises
one or more first metal nitride layers; and
wherein a second bottom electrode of a second subpixel of the plurality of subpixels comprises
one or more second metal nitride layers.
Examiner notes that while there are embodiments within the prior art, see Kobayashi par. 92, that teach the introduction of a silicon nitride layer on a pixel electrode in order to maintain a constant thickness among a variety of pixels, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that a first bottom electrode of a first subpixel of the plurality of subpixels comprises one or more first metal nitride layers and a second bottom electrode of a second subpixel of the plurality of subpixels comprises one or more second metal nitride layers in addition with the other limitations of the independent claim.
Examiner additionally notes par. 61 of the specification which describes the difference in performance associated with the allowable subject matter.
Regarding claim 18, the closest prior art (US20110241000A1, US20100051973A1, US20190165026A1) teaches the method of claim 15.
However, the closest prior art does not teach in combination with the other claimed elements
wherein forming the first closed-loop recess comprises forming the first closed-loop recess such that the first closed-loop recess extends into the first electrode.
Examiner notes that while there are embodiments within the prior art, see Choi figs. 13-14, that teach an isolation structure 60 that extends between electrodes of adjacent pixels, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that the first closed-loop recess is formed such that the first closed-loop recess extends into the first electrode in addition with the other limitations of the independent claim.
Examiner additionally notes par. 46 of the specification which describes the difference in performance associated with the allowable subject matter.
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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