DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/01/2024 and 02/19/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the first semiconductor wafer and second semiconductor wafer" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. There is no prior recitation of “a first semiconductor wafer” or “a second semiconductor wafer” in claim 12, or in claim 7 on which claim 12 depends. Rather, “a first electrical component” and “a second electrical component” are introduced in claim 7, rendering it unclear if the respective “semiconductor wafer(s)” of claim 12 correspond to these “electrical components” or other elements. Therefore, for the purposes of Examination, Examiner has interpreted "the first semiconductor wafer and second semiconductor wafer" in claim 12 as --- the first electrical component and the second electrical component --- however, this edit may be altered if Applicant intends otherwise.
Claim 13 recites the limitation "the first semiconductor wafer and second semiconductor wafer" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. There is no prior recitation of “a first semiconductor wafer” or “a second semiconductor wafer” in claim 13, or in claim 7 on which claim 13 depends. Rather, “a first electrical component” and “a second electrical component” are introduced in claim 7, rendering it unclear if the respective “semiconductor wafer(s)” of claim 13 correspond to these “electrical components” or other elements. Therefore, for the purposes of Examination, Examiner has interpreted "the first semiconductor wafer and second semiconductor wafer" in claim 13 as --- the first electrical component and the second electrical component --- however, this edit may be altered if Applicant intends otherwise.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7-11, 14-17, 20, and 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lo (U.S. PG Pub No US2019/0239361A1) in view of Wong (U.S. PG Pub No US2015/0056819A1).
Regarding claim 1, Lo teaches a method [see fig. 3, 0024] of making a semiconductor device (300) fig. 3 [0025], comprising:
providing a first substrate (comprising 320) fig. 3 [0024];
providing a second substrate (comprising 310) fig. 3 [0024] (310 acting as substrate hosting 312); and
forming an interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] (copper layers 316, 326 with 312 and 322 forming parts of conductive interconnect structure [0024, 0027]) between (vertically between) the first substrate (320) and second substrate (310) using a microwave (360) (pulsed microwave [see fig. 3, 0024]).
However, Lo does not explicitly disclose using a variable frequency microwave (360) ([0024] suggests microwave radiation may be pulsed, however, does not explicitly disclose frequency characteristics or changing microwave frequencies).
Wong teaches a method [see fig. 1, 0032] comprising using a variable frequency microwave (112 from 110) fig. 1 [0037-0039].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of forming the structure of Lo such that the microwave radiation is provided [0037] as variable frequency microwave energy [0039] at a range of distinct frequencies [0013-0014, 0039] in order to improve control over the heating temperature of the target material(s) [0013-0017] and reduce the potential of arcing and subsequent damage [0038], as taught by Wong.
Regarding claims 2 and 3, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 1. Lo in view of Wong also teaches further including applying heat and pressure [see fig. 3, 0024] (‘heat’ [0024] from radiation and ‘compressive force’ pressure [0024]) to the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] while using the variable frequency microwave (360) fig. 3 [0024] (modified by Wong to have variable frequency [0037-0039 Wong]).
Regarding claim 4, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 1. Lo also teaches wherein the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] includes a bump (312) fig. 3 [0024].
Regarding claim 7, Lo teaches a method [see fig. 3, 0024] of making a semiconductor device (300) fig. 3 [0025], comprising:
providing a first electrical component (comprising 320) fig. 3 [0024] (substrate) [0015];
providing a second electrical component (comprising 310) fig. 3 [0024] (die) [0015]; and
forming an interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] (copper layers 316, 326 with 312 and 322 forming parts of conductive interconnect structure [0024, 0027]) between (vertically between) the first electrical component (320) and second electrical component (310) using a microwave (360) [see fig. 3, 0024] (pulsed microwave radiation 360 [0024]).
However, Lo does not explicitly disclose using a variable frequency microwave (360) ([0024] suggests microwave radiation may be pulsed, however, does not explicitly disclose frequency characteristics or changing microwave frequencies).
Wong teaches a method [see fig. 1, 0032] comprising using a variable frequency microwave (112 from 110) fig. 1 [0037-0039].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of forming the structure of Lo such that the microwave radiation is provided [0037] as variable frequency microwave energy [0039] at a range of distinct frequencies [0013-0014, 0039] in order to improve control over the heating temperature of the target material(s) [0013-0017] and reduce the potential of arcing and subsequent damage [0038], as taught by Wong.
Regarding claim 9, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 7. Lo also teaches wherein the first electrical component (comprising 320) fig. 3 [0024] (substrate) [0015] includes an interconnect substrate (320 is a substrate [0024, 0015] that directly hosts interconnect components (such as 322, 326) [0024, 0027] on its surface).
Regarding claims 10 and 11, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 7. Lo in view of Wong also teaches further including applying heat and pressure [see fig. 3, 0024] (‘heat’ [0024] from radiation and ‘compressive force’ pressure [0024]) to the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] while using the variable frequency microwave (360) fig. 3 [0024] (modified by Wong to have variable frequency [0037-0039 Wong]).
Regarding claim 14, Lo teaches a semiconductor device (300) fig. 3 [0025], comprising:
a first substrate (comprising 320) fig. 3 [0024];
a second substrate (comprising 310) fig. 3 [0024] (310 acting as substrate hosting 312); and
an interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] (copper layers 316, 326 with 312 and 322 forming parts of conductive interconnect structure [0024, 0027]) formed between (vertically between) the first substrate (320) and second substrate (310) with a microwave (360) [see fig. 3, 0024] (pulsed microwave radiation 360 [0024]).
However, Lo does not explicitly disclose using a variable frequency microwave (360) ([0024] suggests microwave radiation may be pulsed, however, does not explicitly disclose frequency characteristics or changing microwave frequencies).
Wong teaches a semiconductor structure (100) fig. 1 [0032-0033] comprising a variable frequency microwave (112 from 110) fig. 1 [0037-0039].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of forming the structure of Lo such that the microwave radiation is provided [0037] as variable frequency microwave energy [0039] at a range of distinct frequencies [0013-0014, 0039] in order to improve control over the heating temperature of the target material(s) [0013-0017] and reduce the potential of arcing and subsequent damage [0038], as taught by Wong.
Regarding claim 15, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 14. Lo also teaches further including a thermal-compression block (328) fig. 3 [0025] (thermal-control block 328 [0025] used during heating and compression [0024]), wherein the first substrate (comprising 320) fig. 3 [0024] is attached to the thermal-compression block (328).
Regarding claim 16, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 14. Lo also teaches further including a thermal block (318) fig. 3 [0025] (thermal-control block 318 [0025] used during heating [0024]), wherein the second substrate (comprising 310) fig. 3 [0024] is attached to the thermal block (318).
Regarding claim 17, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 14. Lo also teaches wherein the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] includes a bump (312) fig. 3 [0024].
Regarding claim 20, Lo teaches a semiconductor device (300) fig. 3 [0025], comprising:
a first electrical component (comprising 320) fig. 3 [0024] (substrate) [0015];
a second electrical component (comprising 310) fig. 3 [0024] (die) [0015]; and
an interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] (copper layers 316, 326 with 312 and 322 forming parts of conductive interconnect structure [0024, 0027]) formed between (vertically between) the first electrical component (320) and second electrical component (310) with a microwave (360) [see fig. 3, 0024] (pulsed microwave radiation 360 [0024]).
However, Lo does not explicitly disclose using a variable frequency microwave (360) ([0024] suggests microwave radiation may be pulsed, however, does not explicitly disclose frequency characteristics or changing microwave frequencies).
Wong teaches a semiconductor structure (100) fig. 1 [0032-0033] comprising a variable frequency microwave (112 from 110) fig. 1 [0037-0039].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of forming the structure of Lo such that the microwave radiation is provided [0037] as variable frequency microwave energy [0039] at a range of distinct frequencies [0013-0014, 0039] in order to improve control over the heating temperature of the target material(s) [0013-0017] and reduce the potential of arcing and subsequent damage [0038], as taught by Wong.
Regarding claim 22, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 20. Lo also teaches wherein the first electrical component (comprising 320) fig. 3 [0024] (substrate) [0015] includes an interconnect substrate an interconnect substrate (320 is a substrate [0024, 0015] that directly hosts interconnect components (such as 322, 326) [0024, 0027] on its surface).
Regarding claim 23, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 20. Lo also teaches further including a thermal-compression block (328) fig. 3 [0025] (thermal-control block 328 [0025] used during heating and compression [0024]), wherein the first electronical component (comprising 320) fig. 3 [0024] is attached to the thermal-compression block (328).
Regarding claim 24, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 20. Lo also teaches further including a thermal block (318) fig. 3 [0025] (thermal-control block 318 [0025] used during heating [0024]), wherein the second electrical component (comprising 310) fig. 3 [0024] is attached to the thermal block (318).
Regarding claim 25, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 20. Lo also teaches wherein the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] includes a bump (312) fig. 3 [0024].
Claims 5-6, 12-13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lo (U.S. PG Pub No US2019/0239361A1) modified by Wong (U.S. PG Pub No US2015/0056819A1), as applied in claims 1, 7, and 14 above, and further in view of Kwon (U.S. PG Pub No US2019/0122899A1).
Regarding claim 5, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 1. However, Lo does not explicitly disclose further including forming a non-conductive film around the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between the first substrate (comprising 320) fig. 3 [0024] and second substrate (comprising 310) fig. 3 [0024].
Kwon teaches a method [0027] of forming a semiconductor device (100) fig. 14 [0101] further including forming a non-conductive film (130) fig. 10 [0086-0087] (epoxy flux non-electrically conductive ‘insulating’ paste) [0087] around (laterally around) the interconnect structure (comprising 113, 113a, 121) fig. 11 [0038, 0080, 0091] (see also fig. 14) between (vertically between) the first substrate (124) fig. 14 [0099] and second substrate (110) fig. 14 [0090].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Lo such that the interconnect component(s) are surrounded by an epoxy underfill material [0087-0089] between the substrates [0089] in order to prevent the formation of undesirable bubbles [0092] during processing – thereby improve electrical stability [0092] of the electrical components [0092], as taught by Kwon.
Regarding claim 6, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 1. Lo also teaches further including forming an/a flux material (340) fig. 3 [0024] around (laterally around) the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between (vertically between) the first substrate (comprising 320) fig. 3 [0024] and second substrate (comprising 310) fig. 3 [0024].
However, Lo does not explicitly disclose further including forming an epoxy material around the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between the first substrate (comprising 320) fig. 3 [0024] and second substrate (comprising 310) fig. 3 [0024].
Kwon teaches a method [0027] of forming a semiconductor device (100) fig. 14 [0101] further including forming an epoxy [0087] and flux [0087] material (130) fig. 10 [0086-0087] (“epoxy flux paste” 130 material portions) [0087] around (laterally around) the interconnect structure (comprising 121) fig. 14 [0080, 0091] between (vertically between) the first substrate (124) fig. 14 [0099] and second substrate (110) fig. 14 [0090].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Lo such that the interconnect component(s) are surrounded by an epoxy underfill material [0087-0089] between the substrates [0089] in order to prevent the formation of undesirable bubbles [0092] during processing – thereby improve electrical stability [0092] of the electrical components [0092], as taught by Kwon.
Regarding claim 12, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 7. However, Lo does not explicitly disclose further including forming a non-conductive film around the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between the first electrical component (comprising 320) fig. 3 [0024] and second electrical component (comprising 310) fig. 3 [0024].
Kwon teaches a method [0027] of forming a semiconductor device (100) fig. 14 [0101] further including forming a non-conductive film (130) fig. 10 [0086-0087] (epoxy flux non-electrically conductive ‘insulating’ paste) [0087] around (laterally around) the interconnect structure (comprising 113, 113a, 121) fig. 11 [0038, 0080, 0091] (see also fig. 14) between (vertically between) the first electrical component (124 with 125 of 120) fig. 14 [0099, 0047-0049, 0101] and second electrical component (110) fig. 14 [0090] (chip [0034-0036]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Lo such that the interconnect component(s) are surrounded by an epoxy underfill material [0087-0089] between the substrates [0089] in order to prevent the formation of undesirable bubbles [0092] during processing – thereby improve electrical stability [0092] of the electrical components [0092], as taught by Kwon.
Regarding claim 13, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 7. Lo also teaches further including forming an/a flux material (340) fig. 3 [0024] around (laterally around) the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between (vertically between) the first electrical component (comprising 320) fig. 3 [0024] and second electrical component (comprising 310) fig. 3 [0024].
However, Lo does not explicitly disclose further including forming an epoxy material around the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between the first electrical component (comprising 320) fig. 3 [0024] and second electrical component (comprising 310) fig. 3 [0024].
Kwon teaches a method [0027] of forming a semiconductor device (100) fig. 14 [0101] further including forming an epoxy [0087] and flux [0087] material (130) fig. 10 [0086-0087] (“epoxy flux paste” 130 material portions) [0087] around (laterally around) the interconnect structure (comprising 121) fig. 14 [0080, 0091] between (vertically between) the first electrical component (124 with 125 of 120) fig. 14 [0099, 0047-0049, 0101] and second electrical component (110) fig. 14 [0090] (chip [0034-0036]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Lo such that the interconnect component(s) are surrounded by an epoxy underfill material [0087-0089] between the substrates [0089] in order to prevent the formation of undesirable bubbles [0092] during processing – thereby improve electrical stability [0092] of the electrical components [0092], as taught by Kwon.
Regarding claim 18, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 14. However, Lo does not explicitly disclose further including a non-conductive film formed around the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between the first substrate (comprising 320) fig. 3 [0024] and second substrate (comprising 310) fig. 3 [0024].
Kwon teaches a semiconductor device (100) fig. 14 [0101] further including a non-conductive film (130) fig. 14 [0086-0087] (epoxy flux non-electrically conductive ‘insulating’ paste) [0087] formed (laterally) around the interconnect structure (comprising 113, 113a, 121) fig. 14 [0038, 0080, 0091] between the first substrate (124) fig. 14 [0099] and second substrate (110) fig. 14 [0090].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Lo such that the interconnect component(s) are surrounded by an epoxy underfill material [0087-0089] between the substrates [0089] in order to prevent the formation of undesirable bubbles [0092] during processing – thereby improve electrical stability [0092] of the electrical components [0092], as taught by Kwon.
Regarding claim 19, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 14. Lo also teaches further including an/a flux material (340) fig. 3 [0024] formed around (laterally around) the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between (vertically between) the first substrate (comprising 320) fig. 3 [0024] and second substrate (comprising 310) fig. 3 [0024].
However, Lo does not explicitly disclose further including an epoxy material formed around the interconnect structure (comprising 312 with 322 with 316 with 326) fig. 3 [0024-0025] between the first substrate (comprising 320) fig. 3 [0024] and second substrate (comprising 310) fig. 3 [0024].
Kwon teaches a semiconductor device (100) fig. 14 [0101] further including an epoxy [0087] and a flux [0087] material (130) fig. 14 [0086-0087] (“epoxy flux paste” 130 material portions) [0087] formed (laterally) around the interconnect structure (comprising 121) fig. 14 [0080, 0091] between the first substrate (124) fig. 14 [0099] and second substrate (110) fig. 14 [0090].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Lo such that the interconnect component(s) are surrounded by an epoxy underfill material [0087-0089] between the substrates [0089] in order to prevent the formation of undesirable bubbles [0092] during processing – thereby improve electrical stability [0092] of the electrical components [0092], as taught by Kwon.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lo (U.S. PG Pub No US2019/0239361A1) modified by Wong (U.S. PG Pub No US2015/0056819A1), as applied in claim 7 above, and further in view of Yang (U.S. PG Pub No US2008/0083980A1).
Regarding claim 8, Lo in view of Wong teaches the method [see fig. 3, 0024] of claim 7. However, Lo does not explicitly disclose wherein the first electrical component (comprising 320) fig. 3 [0024] (substrate) [0015] includes a semiconductor wafer (“wafer” not explicitly disclosed).
Yang teaches a method [see title, fig. 2, 0031-0033] wherein the first electrical component (comprising 2) fig. 2 [0033] (substrate) [0033] includes a semiconductor wafer (may be wafer type [0033] of silicon semiconductor [0032]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Lo such that the substrate is provided as a wafter type [0033] in the wafer level packaging technique of Yang [0004, 0005, 0033] in order to improve device reliability [0003, 0011] and improve device miniaturization [0005, 0003, 0011], as taught by Yang.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lo (U.S. PG Pub No US2019/0239361A1) modified by Wong (U.S. PG Pub No US2015/0056819A1), as applied in claim 20 above, and further in view of Chen (U.S. PG Pub No US2022/0238484A1).
Regarding claim 21, Lo in view of Wong teaches the semiconductor device (300) fig. 3 [0025] of claim 20. However, Lo does not explicitly disclose wherein the first electrical component (comprising 320) fig. 3 [0024] (substrate) [0015] includes a semiconductor substrate (semiconductor material not explicitly disclosed for substrate 320 [0015, 0024]).
Chen teaches a semiconductor device (500) fig. 13 [0055] wherein the first electrical component (comprising 302) fig. 13 [0047-0049] (substrate) [0047] includes a semiconductor substrate [0047] (302 formed of semiconductor material such as silicon [0047]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the first electrical component of Lo, a “substrate” [0015, 0024 Lo], to be explicitly formed of a semiconductor material like silicon [0047] in order to satisfy the functional requirements of a variety of devices which could be formed in the first electrical component substrate [0048] and reliably host the formation of additional interconnect structures in the semiconductor substrate [0049], as taught by Chen.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are each considered relevant to the present disclosure because they all feature multiple stacked substrates/electrical components with interconnect structures, i.e, bumps, provided therebetween.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 07/07/2026
