DETAILED ACTION
Double Patenting
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/01/24, 01/02/25, 02/19/26 were filed on/after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,094,838. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of U.S. Patent No. 12,094,838 disclose all limitations cited in claims 1-20 of present application.
Regarding claim 1, Claims 1, 18-19 of ‘838 discloses a semiconductor structure, comprising: a semiconductor substrate comprising a semiconductor material over a base substrate, wherein the substrate comprises one or more sidewalls forming a crack stop trench laterally between a central region of the substrate and a peripheral region of the substrate that surrounds the central region, and wherein the peripheral region of the substrate comprises a plurality of cracks (lines 18-32, Col. 19).
Regarding claim 2, Claim 4 of ‘838 discloses a semiconductor structure, comprising: wherein the base substrate is a silicon wafer having a circular shape (lines 43-45, Col. 19).
Regarding claim 3, 4, 7, claims 1-20 of ‘838 didn’t mention about the distance from an outermost to the crack stop trench and the depth of the trench. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 6, Claims 1, 3 of ‘838 discloses wherein one or more of the plurality of cracks respectively extend between an outermost perimeter of the substrate and the crack stop trench.
Regarding claim 8, Claims 1, 18-19 of ‘838 discloses a semiconductor structure, comprising: a base substrate, one or more materials disposed over the base substrate, and one or more dielectric materials disposed within a crack stop trench formed by sidewalls of the base substrate and the one or more semiconductor materials, the sidewalls being laterally between a central region of the one or more semiconductor materials and a peripheral region of the one or more semiconductor materials surrounding the central region (lines 18-32, Col. 19).
Regarding claim 9, Claim 5 of ‘838 discloses a semiconductor structure wherein the one or more semiconductor materials comprise gallium nitride (lines 46-48, Col. 19).
Regarding claim 10, Claims 1, 5, 6 of ‘838 discloses a GaN on substrate, AlGaN on GaN layer, doped GaN over AlGaN, wherein the crack stop trench extends through the GaN and other layers.
Regarding claim 11, Claims 1-2 of ‘838 disclose wherein the crack stop trench surrounds a plurality of die regions respectively comprising one or more transistor devices (central region comprising semiconductor devices).
Regarding claim 12, Claim 12 of ‘838 discloses wherein the crack stop trench surrounds a plurality of die regions, the plurality of die regions respectively including a seal-ring structure surrounding a device region.
Regarding claim 13, Claim 8 of ‘838 disclose wherein one or more dielectric materials continuously extend from over the one or more semiconductor to within the crack stop trench.
Regarding claim 14, Claim 11 of ‘838 discloses wherein one or more dielectric includes an oxide and a nitride disposed over the oxide.
Regarding claim 15, Claims 1, 18-19 of ‘838 discloses a semiconductor structure, comprising: a semiconductor substrate, wherein the semiconductor substrate comprises one or more sidewalls forming a crack stop trench between a central region of the substrate and a peripheral region of the semiconductor substrate laterally surrounding the central region, a plurality of cracks arrange within the peripheral region and continuously extending from an outermost perimeter of the substrate to terminate at the crack stop trench (lines 35-67, Col. 20).
Regarding claim 16, the claims of the ‘838 disclose a plurality of cracks arranged within the peripheral region of the substrate but fails to mention that two or more of the cracks extend parallel to one another in a plan view. However, it would have been obvious to one having ordinary skill in art at the time the invention was made to have one or more of the cracks to extend parallel to one another, since selecting the relative orientation of the cracks would have constituted a predictable variation of the arrangement where the parallel orientation has not been shown to provide a new or unexpected result.
Regarding claim 17, Claims 1-20 of ‘838 don’t mentions wherein the crack stop trench has a larger width than respective ones of the plurality of cracks. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the widths of the crack stop trench and cracks, including providing the crack stop trench with a width greater than the widths of the cracks, since a change in relative dimension that does not result in a different function of unexpected result is considered an obvious and unpatentable.
Regarding claim 18, Claims 1-20 of ‘838 don’t mention wherein the plurality of cracks include cracks extending to different depths within the semiconductor substrate. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have cracks extending to different depths within the substrate, since the varying crack depth would have been an ordinary dimensional variation and would not change the function of the device.
Regarding claim 19, Claims 6-8 of ‘838 discloses the substrate includes a plurality of different semiconductor materials (Claims 5-6: GaN layer, AlGaN layer …) and the cracks extending through the plurality of different semiconductor materials (Claims 7-8: he cracks extending through those layers).
Regarding claim 20, Claims 1, 4, and 18 of ‘383 discloses the crack stop trench continuously extends in a circular loop that wraps the central region, and the peripheral region has a ring shape that wraps around the crack stop trench.
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,094,838, in view of Lai et al., U.S. Patent No. 9,601,436.
Regarding claim 5, Claims 1-20 of ‘838 fail to disclose one or more wafer identification marks or one or more alignment marks disposed within the peripheral region of the substrate. However, Lai discloses a semiconductor wafer having a wafer identification formed on an edge region and an alignment mark formed on the edge region (Claim 8 of Lai). It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide the wafer identification and/or alignment marks as in Lai in the peripheral region in order to facilitate identification and/or alignment of the semiconductor wafer during the performing an alignment process during semiconductor processing.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached M-F 9am-8pm Flex.
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/THAO P LE/Primary Examiner, Art Unit 2818
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