Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 8 and 15
b. Pending: 1-20
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 10/17/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The Replacement Drawing for Fig. 1 was received on 8/28/2024. The drawing is accepted.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: End-of-Cycle signal generation circuit and method with inverter and transistor coupled in a loopback path.
Amendments to the Specification for paragraphs [0014], [0030], [0035], [0037], [0044] and [0072] are accepted.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01.
Claim 15 recites: “receiving a clock signal and a delayed clock signal at a first logic gate of a signal generator”. How these two clock signals are connected and to which input terminals of the first logic gate, need to be clarified.
Claim 15 further recites: “receiving, at a second logic gate, the second internal clock signal from the second end of the loopback path, and the clock signal”. How these two signals are connected and to which input terminals of the second logic gate, need to be clarified.
Claims 16 and 19-20 all carry the same deficit and henceforth rejected.
Allowable Subject Matter
Claims 1-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
“an inverter comprising an output terminal coupled to a first end of the loopback path; a transistor coupled between a second end of the loopback path and a power distribution node; a buffer comprising an input terminal configured to receive a clock signal; a first logic gate comprising: a first input terminal coupled to the buffer input terminal; a second input terminal coupled to an output terminal of the buffer; and an output terminal coupled to an input terminal of the inverter and a gate of the transistor; and a second logic gate comprising: a first input terminal coupled to the buffer input terminal; a second input terminal coupled to the second end of the loopback path; and an output terminal configured to output an output signal”.
Claims 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Strzelecki et al. (US 20160218724)
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 2/6/2026
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