DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed April 20, 2026.
Claims 1-14 and 16-21 are pending. Claim 15 is canceled. Claim 12 is amended. Claim 21 is new. Claims 1, 12 and 19 are independent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-13, 14, 16-17 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Osada et al. (U.S. 2018/0012640; hereinafter “Osada”).
Regarding independent claim 1, Osada discloses a memory circuit (Fig. 3), comprising:
a memory array (Fig. 3: 11a) comprising a plurality of non-volatile memory cells (Fig. 5: MCs), wherein the non-volatile memory cells are arranged along a plurality of first access lines (Fig. 5: LBLs) and a plurality of second access lines (Fig. 5: LSLs), the first access lines and second access lines each extending along a lateral direction across the memory array (see Fig. 5);
a first access circuit physically disposed on a first side of the memory array in the lateral direction (Fig. 3: element 17 on the bottom side of 11a); and
a second access circuit physically disposed on a second side of the memory array in the lateral direction, wherein the second side is opposite to the first side (Fig. 3: element 17 on the top side of 11a);
wherein the first access circuit is configured to couple a programming voltage to each of the non-volatile memory cells through a corresponding one of the first access lines and provide a first conduction path through a corresponding one of the second access lines, and the second access circuit is configured to provide a second conduction path through the corresponding second access lines (Elements 17 shown in Figures 3 and 5 selectively connect global bit line and source line from the sense amplifier write driver 18 to local bit line and source line, see page 3, par. 0053-0054. The write driver is connected to the bit lines to pass a current through the memory cell, see page 2, par. 0038).
Regarding claim 2, Osada discloses wherein each of the non-volatile memory cells comprises an access transistor and a resistor coupled to each other in series (Fig. 2: 23 coupled in series with 22), in which the resistor is configured to store at least a data bit (see page 2, par. 0031).
Regarding claim 3, Osada discloses wherein each of the non-volatile memory cells comprises an access transistor and a capacitor coupled to each other in series, in which the capacitor is configured to store at least a data bit (The embodiments described by Osada are applicable to various types of semiconductor storage devices such as volatile memory, and one of volatile memory is a DRAM which comprises a capacitor and a transistor, see page 1, par. 0003 and page 10, par. 0203).
Regarding claim 4, Osada discloses wherein the first conduction path extends from the corresponding non-volatile memory cell, through a first transistor and a second transistor, to ground (Fig. 5 shows a conduction path that goes from first MC coupled to LBL1 to transistor 24-1, transistor 25 and ground), and the second conduction path extends from the corresponding non-volatile memory cell, through a third transistor, to ground(Fig. 5: shows another conduction path that goes from first MC coupled to LSL1 to transistor 26-1, transistor 27 and ground).
Regarding claim 5, Osada discloses wherein the first access circuit includes the first and second transistors (Fig. 5: 17a comprises 24-1 and 25), and the second access circuit includes the third transistor(Fig. 5: 17b comprises 27).
Regarding claim 7, Osada discloses wherein one source/drain terminal of the first transistor is connected to the second access line (Fig. 5: one source/drain terminal of 24-1 is electrically connected to LSL1 through the memory cell MC), with one source/drain terminal of the second transistor connected to the ground (Fig. 5: one source/drain terminal of 25 is connected to ground).
Regarding claim 8, Osada discloses wherein one source/drain terminal of the third transistor is connected to the second access line (Fig. 5: one source/drain terminal of 27 is connected to LSL1), with the other source/drain terminal of the third transistor connected to the ground (Fig. 5: one source/drain terminal of 27 connected to ground).
Regarding claim 9, Osada discloses wherein when each of the non-volatile memory cells is configured to be programmed by a current flowing through the corresponding first access line and the non-volatile memory cell itself, the current is configured to break into two separated currents flowing through the first conduction path and the second conduction path, respectively (Fig. 2 shows that a current can flow from BL to SL to write “0” and the current break into the input current and the output current, see page 3, par. 0047).
Regarding claim 10, Osada discloses wherein the non-volatile memory cell is configured to be programmed from a first resistance state to a second resistance state (see page 3, par. 0047).
Regarding claim 11, Osada discloses a third access circuit physically disposed on a middle of the memory array in the lateral direction, wherein the third access circuit is configured to provide a third conduction path through the corresponding second access lines (Fig. 3: 17 physically disposed on a middle of 11a).
Regarding independent claim 12, Osada discloses a memory circuit (Fig. 3), comprising:
a memory cell (Fig. 5: MCs) coupled between a first access line and a second access line, wherein the first access line (Fig. 5: LBLs) and the second access line (Fig. 5: LSLs) both extend along a lateral direction;
a first access circuit physically disposed on a first side of the memory cell in the lateral direction (Fig. 3: element 17 on the bottom side of 11a), wherein the first access circuit comprises a first sub-circuit and a second sub-circuit (Fig. 5: 17a comprises 24-1 and 25); and
a second access circuit physically disposed on a second side of the memory cell in the lateral direction, the second side being opposite to the first side (Fig. 3: element 17 on the top side of 11a), wherein the second access circuit comprises a third sub-circuit and a fourth sub-circuit (Fig. 5: 17b comprises 26-1 and 27);
wherein the first sub-circuit is configured to coupled a programming voltage to the memory cell through the first access line (Elements 17 shown in Figures 3 and 5 selectively connect global bit line and source line from the sense amplifier write driver 18 to local bit line and source line, see page 3, par. 0053-0054. The write driver is connected to the bit lines to pass a current through the memory cell, see page 2, par. 0038), the second and third sub-circuits are each configured to provide a respective conduction path from the memory cell to ground (Fig. 5: transistors 24-1 and 26-1 provide a conduction path from the memory cell and are electrically connected to ground through transistor 25), while the fourth sub-circuit being deactivated (Fi. 5: to apply a signal to the memory cell from GSL transistor 27 is deactivated),
wherein the first sub-circuit is configured to provide a first conduction path through the second access line (Fig. 5: 21-1 provide a conduction path through MC and LSL1), and the third sub-circuit is configured to provide a second conduction path through the second access line (Fig. 5: 26-1 provide another conduction path through LSL1).
Regarding claim 13, Osada discloses wherein the memory cell comprises an access transistor and a resistor coupled to each other in series (Fig. 2: 23 coupled in series with 22), in which the resistor is configured to store at least a data bit (see page 2, par. 0031).
Regarding claim 14, Osada discloses wherein the memory cell comprises an access transistor and a capacitor coupled to each other in series, in which the capacitor is configured to store at least a data bit (The embodiments described by Osada are applicable to various types of semiconductor storage devices such as volatile memory, and one of volatile memory is a DRAM which comprises a capacitor and a transistor, see page 1, par. 0003 and page 10, par. 0203).
Regarding claim 16, Osada discloses wherein the first conduction path extends from the memory cell, through a first transistor and a second transistor, to ground (Fig. 5 shows a conduction path that goes from first MC coupled to LBL1 to transistor 24-1, transistor 25 and ground), and the second conduction path extends from the memory cell, through a third transistor, to ground(Fig. 5: shows another conduction path that goes from first MC coupled to LSL1 to transistor 26-1, transistor 27 and ground).
Regarding claim 17, Osada discloses wherein the first access circuit includes the first and second transistors (Fig. 5: 17a comprises 24-1 and 25), and the second access circuit includes the third transistor(Fig. 5: 17b comprises 27).
Regarding independent claim 19, Osada discloses a method for operating a memory circuit (Fig. 3), comprising:
activating a first access circuit physically disposed on a first side of a memory array (Fig. 3: 11a) in a lateral direction (Fig. 3: element 17 on the bottom side of 11a), wherein the memory array (Fig. 3: 11a) comprises a plurality of non-volatile memory cells (Fig. 5: MCs), wherein the non-volatile memory cells are arranged along a plurality of first access lines (Fig. 5: LBLs) and a plurality of second access lines (Fig. 5: LSLs), the first access lines and second access lines each extending along the lateral direction across the memory array (see Fig. 5);
activating a second access circuit physically disposed on a second side of the memory array in the lateral direction, wherein the second side is opposite to the first side (Fig. 3: element 17 on the top side of 11a);
receiving a first current flowing through the memory array (“a current is detected flowing through the memory cell,” see page 2, par. 0038);
conducting a second current flowing through the first access circuit via a first conduction path (Fig. 2: a current “A2” is applied from the bit line to the memory cell); and
conducting a third current flowing through the second access circuit via a second conduction path (Fig. 2: a current “A1” is applied from the source line to the memory cell),
wherein the first access circuit is configured to coupled a programming voltage to each of the non-volatile memory cells through a corresponding one of the first access lines and provide the first conduction path through a corresponding one of the second access lines, and the second access circuit is configured to provide the second conduction path through the corresponding second access lines (Elements 17 shown in Figures 3 and 5 selectively connect global bit line and source line from the sense amplifier write driver 18 to local bit line and source line, see page 3, par. 0053-0054. The write driver is connected to the bit lines to pass a current through the memory cell, see page 2, par. 0038).
Regarding claim 20, Osada discloses conducting a fourth current flowing through a third access circuit via a third conduction path, wherein the third access circuit is physically disposed on a middle of the memory array in the lateral direction, wherein the third access circuit is configured to provide the third conduction path through the corresponding second access lines (Fig. 3: shows a bit line and source line controller physically disposed on a middle of the memory array, the bit line and source line controller shown in Fig. 3 is identical to the bit line and source line controller shown in Figure 5 which provides currents through conduction paths).
Regarding claim 21, Osada discloses wherein each of the non-volatile memory cells comprises an access transistor and a resistor coupled to each other in series, in which the resistor is configured to store at least a data bit (see page 2, par. 0031).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Osada et al. (U.S. 2018/0012640; hereinafter “Osada”) in view of Chou (U.S. 2017/0263313).
Regarding claim 6, Osada discloses the limitation with respect to claim 4.
However, Osada is silent with respect to the first to third transistors are configured to be concurrently activated, when the programming voltage is applied to corresponding non-volatile memory cell through one of the first access lines.
Similar to Osada, Chou teaches a memory circuit (Fig. 7) comprising a memory array (Fig. 7: 110) comprising a plurality of non-volatile memory cells (Fig. 7: 115), wherein the non-volatile memory cells are arranged along a plurality of first access lines (Fig. 7: BLs) and a plurality of second access lines (Fig. 7: SLs), and first to third transistors (Fig. 7: Ps, Ns and transistors within 130 and 135).
Furthermore, Chou teaches wherein the first to third transistors are configured to be concurrently activated, when the programming voltage is applied to corresponding non-volatile memory cell through one of the first access lines (Fig. 4A: when applying voltage to memory cell 115. PD1, NS1, NS2 and NS3 are concurrently activated).
Since Chou and Osada are from the same field of endeavor, the teachings described by Chou would have been recognized in the pertinent art of Osada.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Chou with the teachings of Osada for the purpose of overcome reliability issues, see Chou’s page 4, par. 0074.
Regarding claim 18, Osada discloses the limitation with respect to claim 16.
However, Osada is silent with respect to the first to third transistors are configured to be concurrently activated, when the programming voltage is applied to corresponding non-volatile memory cell through one of the first access lines.
Similar to Osada, Chou teaches a memory circuit (Fig. 7) comprising a memory array (Fig. 7: 110) comprising memory cell (Fig. 7: 115), wherein the memory cell is coupled between first access lines (Fig. 7: BLs) and second access lines (Fig. 7: SLs), and first to third transistors (Fig. 7: Ps, Ns and transistors within 130 and 135).
Furthermore, Chou teaches wherein the first to third transistors are configured to be concurrently activated, when the programming voltage is applied to corresponding non-volatile memory cell through one of the first access lines (Fig. 4A: when applying voltage to memory cell 115. PD1, NS1, NS2 and NS3 are concurrently activated).
Since Chou and Osada are from the same field of endeavor, the teachings described by Chou would have been recognized in the pertinent art of Osada.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Chou with the teachings of Osada for the purpose of overcome reliability issues, see Chou’s page 4, par. 0074.
Response to Arguments
Applicant's arguments filed with respect to claim 1 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserts that Osada fails to disclose the first access circuit is configured to…provide a first conduction path through a corresponding one of the second access lines, because Osada at no point contemplates any dual-side discharge configuration having first and second access circuit that both provides path through corresponding second access lines, see Applicant’s Remarks pages 8-9. This particular remark is not considered persuasive.
Osada’s Figure 5 shows access circuits 17a and 17b and when the first access line “LBL” is selected and one of the memory cell is selected by the word line, a conduction path is provided in LBL and also in LSL through the selected memory cells and access transistor. While raising an interesting point, Claim 1 requires just a “path” through the second access lines. The claimed apparatus does not appear to require a dual-side discharge configuration having first and second access circuit discharging or transferring either “a current” or “a voltage” through the “path” provided by the second access lines. This remark appears to be directed to subject matter not present in the claims.
For the above reasons, the previously applied rejections are considered proper and maintained.
The other claims were argued for substantially the same reasons as claim 1, and the arguments are not persuasive for the same reasons.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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