DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 5 and 13 are objected to because of the following informalities:
In claim 5 ll. 6, after “vertical interfaces with” remove the period “.”.
In claim 13 after “claim 9” insert a comma --,--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 8-9, 11, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yeo (US 2018/0151683) in view of Cheng (US 8,536,632).
With regards to claim 1, fig. 8 of Yeo discloses a device comprising: a plurality of isolation regions 58 comprising a first portion (58 between left and right 52) and a second portion (leftmost 58); a semiconductor strip (left 52) between and contacting the first portion (58 between left and right 52) and the second portion (leftmost 58); a source/drain region 132 overlapping the semiconductor strip 52, the source/drain region comprising 132: a first semiconductor layer 132 comprising a first part (left 132), wherein the first part (58 between left and right 2) comprises: a first vertical edge (right vertical side of left 132) and a second vertical edge (left vertical side of left 132) of the first semiconductor layer 132; and a first slanted top surface (right angled surface of 132) and a second slanted top surface (left angled surfaces of 132) joining with each other to form a triangle (top angled surfaces of 132), wherein the first slanted top surface (right angled surface of 132) and the second slanted top surface (left angled surface of 132) are connected to the first vertical edge (right vertical surface of 132) and the second vertical edge (left vertical surface of 132), respectively; and a second semiconductor layer 134 on the first part (left 132) of the first semiconductor layer 132.
Yeo does not disclose vertical edges on (110) planes of the first semiconductor layer.
However, fig. 6 of Cheng discloses vertical edges on (110) planes (“{110} plane”, claim col. 7 ll. 22) of the first semiconductor layer 211.
Therefore, it would have been obvious to one of ordinary skill in the art to form the source layers of Yeo with the {110} plane as taught in Cheng in order to form uniform fin structures. See col. 7 ll. 39 of Cheng.
With regards to claim 2, fig. 8 of Yeo disclose that the source/drain region 132 is of n-type (“first n-type epitaxial layer 132”, par [0080]), and the second semiconductor layer 134 comprises a conformal part.
With regards to claim 4, fig. 8 of Yeo discloses that the semiconductor strip comprises silicon (“silicon substrate”, par [0029]), the first semiconductor layer 132 comprises silicon and phosphorous (“SiP”, par [0080]), and wherein the first semiconductor layer 132 extends laterally beyond opposite edges of the semiconductor strip 52.
With regards claim 5, fig. 8 of Yeo discloses an additional semiconductor strip (right 52) separated from the semiconductor strip (left 52) by the first portion of the plurality of isolation regions (58 between 52), wherein the first semiconductor layer 132 further comprises a second part (right 132) comprising: a third vertical edge (left vertical side of right 132) and a fourth vertical edge (right vertical side of right 132) of the first semiconductor layer 132, the second semiconductor layer 134 comprises an intermediate portion (134 between 132) extending between the first vertical edge (right side of left 132) and the third vertical edge (left side of right 132), the second semiconductor layer 134 forming vertical interfaces with the first vertical edge (right vertical side of left 132) and the third vertical edge (left vertical side of right 132). With regard to claim 8, fig. 8 of Yeo discloses that the second part (right 132) of the first semiconductor layer 132 further comprises: a third slanted top surface (top slanted left surface of 132) and a fourth slanted top surface (top slanted right surface of 132) joining with each other to form an additional triangle, wherein the third slanted top surface (top slanted left surface of right 132) and the fourth slanted top surface (top right slanted surface of right 132) are connected to the third vertical edge (left vertical side of right 132) and the fourth vertical edge (right vertical side of right 132), respectively.
With regard to claim 9, fig. 8 of Yeo discloses a device comprising: a plurality of isolation regions 58 comprising a first portion (58 between left and right 52) and a second portion (leftmost 58); a semiconductor strip (left 52) between and contacting the first portion (58 between left and right 52) and the second portion (leftmost 58); a source/drain region 132 overlapping the semiconductor strip 52, the source/drain region 132 comprising: a first semiconductor layer 132 comprising a first part (left 132), wherein the first part (left 132) comprises: a first vertical edge (vertical right side of left 132) and a second vertical edge (vertical left side of left 132) parallel to each other; and a first slanted top surface (right slanted top of left 132) and a second slanted top surface (left slanted top of left 132) joining to the first vertical edge (vertical right side of left 132) and the second vertical edge (vertical left side of left 132), respectively; a second semiconductor layer 134 on the first part of the first semiconductor layer (left 132); and an air gap 224 directly under (portions of 224 on left and right edges under 134) the second semiconductor layer 134.
With regard to claim 11, fig. 8 of Yeo discloses that the source/drain region 132 is of n-type (“n-type epitaxial layer 132”, par [0080]).
With regard to claim 14, fig. 8 of Yeo discloses that the first slanted top surface (right slanted top of left 132) is joined to the second slanted top surface (left slanted top of left 132) to form a triangular shape in a cross-sectional view of the device.
With regard to claim 15, fig. 8 of Yeo discloses that the first semiconductor layer 132 further comprises a second part (right 132) comprising: a third vertical edge (vertical left side of right 132) and a fourth vertical edge (vertical right side of right 132) parallel to the first vertical edge (vertical right side of left 132); and a third slanted top surface (slanted top left of right 132) and a fourth slanted top surface (slanted top right of right 132) joining to the third vertical edge (vertical left side of right 132) and the fourth vertical edge (vertical right side of right 132), respectively.
With regard to claim 16, fig. 8 of Yeo discloses that the second semiconductor layer 134 connects (through 222) the first part (left 132) of the first semiconductor layer 132 to the second part (right 132) of the first semiconductor layer.
With regard to claim 17, fig. 8 of Yeo discloses both of the first part (left 132) and the second part (right 132) of the first semiconductor layer 132 are embedded in the second semiconductor layer 134.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yeo (US 2018/0151683), Cheng (US 8,536,632), and Chang (US 2018/0175172).
With regards to claim 3, Yeo and Cheng do not disclose that the second semiconductor layer has a higher n-type doping concentration than the first semiconductor layer.
However, fig. 13 of Chang discloses that the second semiconductor layer 86 has a higher n-type doping concentration (“second epitaxial layer 86 may have higher doping than the first epitaxial layer 80”, par [0032]) than the first semiconductor layer 80.
Therefore, it would have been obvious to one of ordinary skill in the art to form the second n-type epitaxial layer of Yeo at a higher doping concentration than the underlying layer as taught in Chang in order to provide a lower contact resistance. See par [0032] of Chang.
With regard to claim 12, Yeo and Cheng do not disclose that the second semiconductor layer has a higher n-type doping concentration than the first semiconductor layer.
However, fig. 13 of Chang discloses that the second semiconductor layer 86 has a higher n-type doping concentration (“second epitaxial layer 86 may have higher doping than the first epitaxial layer 80”, par [0032]) than the first semiconductor layer 80.
Therefore, it would have been obvious to one of ordinary skill in the art to form the second n-type epitaxial layer of Yeo at a higher doping concentration than the underlying layer as taught in Chang in order to provide a lower contact resistance. See par [0032] of Chang.
Allowable Subject Matter
Claims 6-7, 10, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, Yeo (US 2018/0151683), Cheng (US 8,536,632), and Chang (US 2018/0175172) do not disclose that the intermediate portion of the second semiconductor layer is over and exposed to the air gap. Claim 7 depends on claim 6 and is objected.
Regarding claim 10, Yeo (US 2018/0151683), Cheng (US 8,536,632), and Chang (US 2018/0175172) do not disclose a bottom surface of the second semiconductor layer is exposed to the air gap.
Regarding claim 13, Yeo (US 2018/0151683), Cheng (US 8,536,632), and Chang (US 2018/0175172) do not disclose wherein the first semiconductor layer has a higher dopant concentration than the third semiconductor layer.
Claims 18-20 are allowed.
Regarding claim 18, Yeo (US 2018/0151683), Cheng (US 8,536,632), and Chang (US 2018/0175172) do not disclose a third semiconductor layer contacting the second semiconductor layer, wherein the first vertical edge of the first part is parallel to, and is spaced apart from, the first vertical edge of the second part by a portion of the third semiconductor layer. Claims 19-20 depend on claim 18 and are allowed.
Conclusion
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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